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| 8-Bit XC87xCLM 8-Bit Single-Chip Microcontroller Data Sheet V1.5 2011-03 Micr o co n t ro ll e rs Edition 2011-03 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2011 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 8-Bit XC87xCLM 8-Bit Single-Chip Microcontroller Data Sheet V1.5 2011-03 Micr o co n t ro ll e rs XC87xCLM XC87x Data Sheet Revision History: V1.5 2011-03 Previous Versions: V1.4 Page Page 3 Subjects (major changes since last revision) A new variant, SAF-XC874CM-13FVA 5V, has been added in Table 2. Changes from V1.4 2010-08 to V1.5 2011-03 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.5, 2011-03 XC87xCLM Table of Contents Table of Contents 1 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.2.1 3.2.1.1 3.2.2 3.2.2.1 3.2.2.2 3.2.3 3.2.3.1 3.2.4 3.2.4.1 3.2.4.2 3.2.4.3 3.2.4.4 3.2.4.5 3.2.4.6 3.2.4.7 3.2.4.8 3.2.4.9 3.2.4.10 3.2.4.11 3.2.4.12 3.2.4.13 3.2.4.14 3.2.4.15 3.3 3.3.1 3.4 3.4.1 3.4.2 3.4.3 3.5 3.6 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Password Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC87x Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer 2 Compare/Capture Unit Registers . . . . . . . . . . . . . . . . . . . . . Timer 21 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MultiCAN Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Bank Pagination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . . I-1 21 21 22 24 24 26 26 28 32 33 34 34 35 36 37 40 40 43 47 49 50 54 54 55 55 57 58 60 61 61 67 69 70 72 Data Sheet V1.5, 2011-03 XC87xCLM Table of Contents 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.10 3.11 3.12 3.13 3.13.1 3.13.2 3.14 3.15 3.15.1 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.22.1 3.22.2 3.23 3.23.1 3.24 4 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.2.3.1 4.2.4 4.3 4.3.1 4.3.2 Data Sheet Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Recommended External Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . 77 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 UART and UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Baud Rate Generation using Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Normal Divider Mode (8-bit Auto-reload Timer) . . . . . . . . . . . . . . . . . . . . . 91 LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . 94 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Timer 2 and Timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Timer 2 Capture/Compare Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Controller Area Network (MultiCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ADC Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ADC Conversion Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Threshold Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-2 108 108 108 109 110 111 111 114 115 117 118 122 122 123 V1.5, 2011-03 XC87xCLM Table of Contents 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 5 5.1 5.2 5.3 Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Data Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package and Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 125 126 128 129 131 133 133 134 136 Data Sheet I-3 V1.5, 2011-03 8-Bit Single-Chip Microcontroller XC87xCLM 1 Summary of Features The XC87x has the following features: * High-performance XC800 Core - compatible with standard 8051 processor - two clocks per machine cycle architecture (for memory access without wait state) - two data pointers * On-chip memory - 8 Kbytes of Boot ROM - 256 bytes of RAM - 3 Kbytes of XRAM - 64/52 Kbytes of Flash; (includes memory protection strategy) * I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (more features on next page) Flash 52K/64K x 8 On-Chip Debug Support UART SSC Port 0 8-bit Digital I/O Boot ROM 8K x 8 XC800 Core XRAM 3K x 8 Capture/Compare Unit 16-bit Port 1 8-bit Digital I/O Compare Unit 16-bit Timer 2 Capture/ Compare Unit 16-bit ADC 10-bit 8-channel . Port 3 8-bit Digital I/O RAM 256 x 8 Timer 0 16-bit Timer 1 16-bit Timer 21 16-bit Port 4 8-bit Digital I/O MDU CORDIC MultiCAN Watchdog Timer UART1 Port 5 8-bit Digital I/O 8-bit Analog Input Figure 1 XC87x Functional Units Data Sheet 1 V1.5, 2011-03 XC87xCLM Summary of Features Features: (continued) * * * * Power-on reset generation Brownout detection for core logic supply On-chip OSC and PLL for clock generation - Loss-of-Clock detection Power saving modes - slow-down mode - idle mode - power-down mode with wake-up capability via RXD or EXINT01) - clock gating control to each peripheral Programmable 16-bit Watchdog Timer (WDT) Five ports - Up to 40 pins as digital I/O - 8 dedicated analog inputs used as A/D converter input 8-channel, 10-bit ADC Four 16-bit timers - Timer 0 and Timer 1 (T0 and T1) - Timer 2 and Timer 21 (T2 and T21) Multiplication/Division Unit for arithmetic operations (MDU) CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear functions MultiCAN with 2 nodes, 32 message objects Two Capture/compare units - Capture/compare unit 6 for PWM signal generation (CCU6) - Timer 2 Capture/compare unit for vaious digital signal generation (T2CCU) Two full-duplex serial interfaces (UART and UART1) Synchronous serial channel (SSC) On-chip debug support - 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) - 64 bytes of monitor RAM Packages: - PG-LQFP-64 - PG-VQFN-48 Temperature range TA: - SAF (-40 to 85 C) - SAX (-40 to 105 C) - SAK (-40 to 125 C) * * * * * * * * * * * * * 1) SAK product variant does not support power-down mode. Data Sheet 2 V1.5, 2011-03 XC87xCLM Summary of Features XC87x Variant Devices The XC87x product family features devices with different configurations, program memory sizes, package options, power supply voltage, temperature and quality profiles (Automotive or Industrial), to offer cost-effective solutions for different application requirements. The list of XC87x device configurations are summarized in Table 1. 2 types of packages are available : * * PG-LQFP-64, which is denoted by XC878 and; PG-VQFN-48, which is denoted by XC874 Device Configuration CAN Module No No Yes No Yes LIN BSL Support No No No Yes Yes MDU Module No Yes Yes Yes Yes Table 1 Device Name XC87x XC87xM XC87xCM XC87xLM XC87xCLM From these 5 different combinations of configuration, each are further made available in many sales types, which are grouped according to device type, program memory sizes, power supply voltage, temperature and quality profiles (Automotive or Industrial), as shown in Table 2. Table 2 Sales Type Device Profile Device Program Type Memory (Kbytes) Flash Flash Flash Flash Flash Flash Flash Flash 52 52 52 64 64 64 52 52 Power TempSupply erature (C) (V) 5.0 5.0 5.0 5.0 5.0 5.0 3.3 3.3 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 Quality Profile Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial SAF-XC878-13FFI 5V SAF-XC878M-13FFI 5V SAF-XC878CM-13FFI 5V SAF-XC878-16FFI 5V SAF-XC878M-16FFI 5V SAF-XC878CM-16FFI 5V SAF-XC878-13FFI 3V3 SAF-XC878M-13FFI 3V3 Data Sheet 3 V1.5, 2011-03 XC87xCLM Summary of Features Table 2 Sales Type Device Profile (cont'd) Device Program Type Memory (Kbytes) Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash 52 64 64 64 52 52 52 52 64 64 64 64 52 52 52 52 64 64 64 64 52 52 52 52 64 64 64 64 64 4 Power TempSupply erature (V) (C) 3.3 3.3 3.3 3.3 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 105 -40 to 105 -40 to 105 -40 to 105 -40 to 105 -40 to 105 -40 to 105 -40 to 105 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 85 Quality Profile Industrial Industrial Industrial Industrial Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive V1.5, 2011-03 SAF-XC878CM-13FFI 3V3 SAF-XC878-16FFI 3V3 SAF-XC878M-16FFI 3V3 SAF-XC878CM-16FFI 3V3 SAF-XC878-13FFA 5V SAF-XC878CM-13FFA 5V SAF-XC878LM-13FFA 5V SAF-XC878CLM-13FFA 5V SAF-XC878-16FFA 5V SAF-XC878CM-16FFA 5V SAF-XC878LM-16FFA 5V SAF-XC878CLM-16FFA 5V SAX-XC878-13FFA 5V SAX-XC878CM-13FFA 5V SAX-XC878LM-13FFA 5V SAX-XC878CLM-13FFA 5V SAX-XC878-16FFA 5V SAX-XC878CM-16FFA 5V SAX-XC878LM-16FFA 5V SAX-XC878CLM-16FFA 5V SAK-XC878-13FFA 5V SAK-XC878CM-13FFA 5V SAK-XC878LM-13FFA 5V SAK-XC878CLM-13FFA 5V SAK-XC878-16FFA 5V SAK-XC878CM-16FFA 5V SAK-XC878LM-16FFA 5V SAK-XC878CLM-16FFA 5V SAF-XC874LM-16FVA 5V Data Sheet XC87xCLM Summary of Features Table 2 Sales Type Device Profile (cont'd) Device Program Type Memory (Kbytes) Flash Flash Flash Flash Flash Flash Flash Flash 64 52 64 64 64 52 52 52 Power TempSupply erature (V) (C) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 -40 to 85 -40 to 85 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 -40 to 125 Quality Profile Automotive Automotive Automotive Automotive Automotive Automotive Automotive Automotive SAF-XC874CM-16FVA 5V SAF-XC874CM-13FVA 5V SAK-XC874LM-16FVA 5V SAK-XC874CM-16FVA 5V SAK-XC874-16FVA 5V SAK-XC874LM-13FVA 5V SAK-XC874CM-13FVA 5V SAK-XC874-13FVA 5V As this document refers to all the derivatives, some description may not apply to a specific product. For simplicity, all versions are referred to by the term XC87x throughout this document. Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies: * * The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery For the available ordering codes for the XC87x, please refer to your responsible sales representative or your local distributor. Data Sheet 5 V1.5, 2011-03 XC87xCLM General Device Information 2 General Device Information Chapter 2 contains the block diagram, pin configurations, definitions and functions of the XC87x. 2.1 Block Diagram The block diagram of the XC87x is shown in Figure 2. XC87x 8-Kbyte Boot ROM1) 256-byte RAM + 64-byte monitor RAM 3-Kbyte XRAM MDU 52/64-Kbyte Flash Clock Generator 4 MHz On-chip OSC PLL WDT OCDS SSC CCU6 Port 4 P4.0 - P4.7 MultiCAN Internal Bus Port 0 P0.0 - P0.7 XC800 Core TMS MBC TM RESET VDDP VSSP VDDC VSSC T0 & T1 UART Port 1 P1.0 - P1.7 CORDIC UART1 Port 3 P3.0 - P3.7 XTAL1 XTAL2 Port 5 Timer 2 Capture/ Compare Unit Timer 21 P5.0 - P5.7 ADC AN0 - AN7 VAREF VAGND 1) Includes 1-Kbyte monitor ROM Figure 2 XC87x Block Diagram Data Sheet 6 V1.5, 2011-03 XC87xCLM General Device Information 2.2 Logic Symbol The logic symbols of the XC878 and XC874 are shown in Figure 3. VDDP VSSP VDDP VSSP Port 0 8-Bit VAREF VAGND RESET MBC TMS TM XTAL1 XTAL2 Port 5 8-Bit AN0 - AN7 XC878 Port 4 8-Bit Port 1 8-Bit VAREF VAGND RESET MBC TMS TM XTAL1 XTAL2 Port 4 4-Bit AN1,AN2, AN4 - AN7 XC874 Port 3 7-Bit Port 0 8-Bit Port 1 8-Bit Port 3 8-Bit VDDC VSSC VDDC VSSC Figure 3 XC878 and XC874 Logic Symbol Data Sheet 7 V1.5, 2011-03 XC87xCLM General Device Information 2.3 Pin Configuration The pin configuration of the XC878, which is based on the PG-LQFP-64, is shown in Figure 4, while that of the XC874, which is based on the PG-VQFN-48 package, is shown in Figure 5. P4.7 P4.6 P4.5 P4.4 P3.1 P3.0 P3.7 P3.6 P4.3 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 AN7 32 31 30 29 28 27 26 XC878 25 24 23 22 21 20 19 18 17 1 2 3 45 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P3.2 P3.3 P3.4 P3.5 RESET VSSP V DDP N.C. TM MBC P4.0 P4.1 P4.2 P0.7 P0.3 P0.4 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VAREF V AGND AN6 AN5 AN4 AN3 VSSP V DDP AN2 AN1 AN0 P0.1 P5.7 P5.6 P0.2 P0.0 P0.5 P0.6 XTAL2 XTAL1 VSSC VDDC VDDP P5.0 P5.1 P1.6 P1.7 P5.2 P5.3 P5.4 P5.5 TMS Figure 4 XC878 Pin Configuration, PG-LQFP-64 Package (top view) Data Sheet 8 V1.5, 2011-03 XC87xCLM General Device Information P3.1 P3.0 P3.6 P4.3 P1.5 P1.4 P1.3 P1.2 P1.1 36 35 34 33 32 31 30 29 28 27 26 25 P3.4 P3.5 RESET VSSP VDDP NC TM MBC P4.0 P4.1 P4.2 P0.7 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 45 6 7 8 9 10 11 12 XC874 24 23 22 21 20 19 18 17 16 15 14 13 AN7 VAREF VAGND AN6 AN5 AN4 V SSP VDDP AN2 AN1 P0.1 P1.0 P3.3 P3.2 P0. 2 P0.3 P0. 4 P0. 5 P0.6 XTAL2 XTAL1 VSSC VD DC P1.6 P1.7 TMS P0.0 Figure 5 XC874 Pin Configuration, PG-VQFN-48 Package (top view) Data Sheet 9 V1.5, 2011-03 XC87xCLM General Device Information 2.4 Pin Definitions and Functions The functions and default states of the XC87x external pins are provided in Table 3. Table 3 Pin Definitions and Functions Type Reset Function State I/O Port 0 Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, UART1, T2CCU, Timer 21, MultiCAN, SSC and External Bus Interface. Note: External Bus Interface is not available in XC874. P0.0 17/12 Hi-Z TCK_0 T12HR_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input CC61_1 Input/Output of Capture/Compare channel 1 CLKOUT_0 Clock Output RXDO_1 UART Transmit Data Output JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input UART Receive Data Input MultiCAN Node 1 Receiver Input Output of Capture/Compare channel 1 Timer 2 External Flag Output CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/Clock Output MultiCAN Node 1 Transmitter Output Symbol Pin Number (LQFP-64 / VQFN-48) P0 P0.1 21/14 Hi-Z TDI_0 T13HR_1 RXD_1 RXDC1_0 COUT61_1 EXF2_1 P0.2 18/13 PU CTRAP_2 TDO_0 TXD_1 TXDC1_0 Data Sheet 10 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State Hi-Z SCK_1 COUT63_1 RXDO1_0 A17 P0.4 64/2 Hi-Z MTSR_1 CC62_1 TXD1_0 A18 P0.5 1/3 Hi-Z MRST_1 EXINT0_0 T2EX1_1 RXD1_0 COUT62_1 A19 P0.6 2/4 PU T2CC4_1 WR SSC Clock Input/Output Output of Capture/Compare channel 3 UART1 Transmit Data Output Address Line 17 Output SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/Compare channel 2 UART1 Transmit Data Output/Clock Output Address Line 18 Output SSC Master Receive Input/Slave Transmit Output External Interrupt Input 0 Timer 21 External Trigger Input UART1 Receive Data Input Output of Capture/Compare channel 2 Address Line 19 Output Compare Output Channel 4 External Data Write Control Output Symbol Pin Number (LQFP-64 / VQFN-48) P0.3 63/1 P0.7 62/48 PU CLKOUT_1 Clock Output T2CC5_1 Compare Output Channel 5 RD External Data Read Control Output Data Sheet 11 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State I/O Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, T2CCU, Timer 21, MultiCAN, SSC and External Bus Interface. Note: External Bus Interface is not available in XC874. P1.0 34/25 PU RXD_0 T2EX_0 RXDC0_0 A8 EXINT3_0 T0_1 TXD_0 TXDC0_0 A9 P1.2 P1.3 36/27 37/28 PU PU SCK_0 A10 MTSR_0 SCK_2 TXDC1_3 A11 P1.4 38/29 PU MRST_0 EXINT0_1 RXDC1_3 MTSR_2 A12 UART Receive Data Input Timer 2 External Trigger Input MultiCAN Node 0 Receiver Input Address Line 8 Output External Interrupt Input 3 Timer 0 Input UART Transmit Data Output/Clock Output MultiCAN Node 0 Transmitter Output Address Line 9 Output SSC Clock Input/Output Address Line 10 Output SSC Master Transmit Output/Slave Receive Input SSC Clock Input/Output MultiCAN Node 1 Transmitter Output Address Line 11 Output SSC Master Receive Input/ Slave Transmit Output External Interrupt Input 0 MultiCAN Node 1 Receiver Input SSC Master Transmit Output/Slave Receive Input Address Line 12 Output Symbol Pin Number (LQFP-64 / VQFN-48) P1 P1.1 35/26 PU Data Sheet 12 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State PU CCPOS0_1 EXINT5_0 T1_1 MRST_2 EXF2_0 RXDO_0 P1.6 10/9 PU CCU6 Hall Input 0 External Interrupt Input 5 Timer 1 Input SSC Master Receive Input/ Slave Transmit Output Timer 2 External Flag Output UART Transmit Data Output Symbol Pin Number (LQFP-64 / VQFN-48) P1.5 39/30 CCPOS1_1 CCU6 Hall Input 1 T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6_0 External Interrupt Input 6 RXDC0_2 MultiCAN Node 0 Receiver Input T21_1 Timer 21 Input CCPOS2_1 CCU6 Hall Input 2 T13HR_0 CCU6 Timer 13 Hardware Run Input T2_1 Timer 2 Input TXDC0_2 MultiCAN Node 0 Transmitter Output P1.5 and P1.6 can be used as a software chip select output for the SSC. P1.7 11/10 PU Data Sheet 13 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State I/O Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, T2CCU, Timer 21, MultiCAN and External Bus Interface. Note: External Bus Interface is not available in XC874. P3.0 43/33 Hi-Z CCPOS1_2 CCU6 Hall Input 1 CC60_0 Input/Output of Capture/Compare channel 0 RXDO1_1 UART1 Transmit Data Output T2CC0_1/ External Interrupt Input 3/T2CCU EXINT3_2 Capture/Compare Channel 0 CCPOS0_2 CCU6 Hall Input 0 CC61_2 Input/Output of Capture/Compare channel 1 COUT60_0 Output of Capture/Compare channel 0 TXD1_1 UART1 Transmit Data Output/Clock Output CCPOS2_2 RXDC1_1 RXD1_1 CC61_0 T2CC1_1/ EXINT4_2 P3.3 50/36 Hi-Z COUT61_0 TXDC1_1 T2CC2_1/ EXINT5_2 A13 CCU6 Hall Input 2 MultiCAN Node 1 Receiver Input UART1 Receive Data Input Input/Output of Capture/Compare channel 1 External Interrupt Input 4/T2CCU Capture/Compare Channel 1 Output of Capture/Compare channel 1 MultiCAN Node 1 Transmitter Output External Interrupt Input 5/T2CCU Capture/Compare Channel 2 Address Line 13 Output Symbol Pin Number (LQFP-64 / VQFN-48) P3 P3.1 44/34 Hi-Z P3.2 49/35 Hi-Z Data Sheet 14 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State Hi-Z CC62_0 RXDC0_1 T2EX1_0 T2CC3_1/ EXINT6_3 A14 P3.5 52/38 Hi-Z COUT62_0 EXF21_0 TXDC0_1 A15 P3.6 P3.7 41/32 42/PU Hi-Z CTRAP_0 EXINT4_0 COUT63_0 A16 Input/Output of Capture/Compare channel 2 MultiCAN Node 0 Receiver Input Timer 21 External Trigger Input External Interrupt Input 6/T2CCU Capture/Compare Channel 3 Address Line 14 Output Output of Capture/Compare channel 2 Timer 21 External Flag Output MultiCAN Node 0 Transmitter Output Address Line 15 Output CCU6 Trap Input External Interrupt Input 4 Output of Capture/Compare channel 3 Address Line 16 Output Symbol Pin Number (LQFP-64 / VQFN-48) P3.4 51/37 Data Sheet 15 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State I/O Port 4 Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, T2CCU, Timer 21, MultiCAN and External Bus Interface. Note: External Bus Interface is not available in XC874. P4.0 59/45 Hi-Z RXDC0_3 CC60_1 T2CC0_0/ EXINT3_1 D0 P4.1 60/46 Hi-Z TXDC0_3 COUT60_1 T2CC1_0/ EXINT4_1 D1 P4.2 61/47 PU EXINT6_1 T21_0 D2 T2EX_1 EXF21_1 COUT63_2 D3 P4.4 45/Hi-Z MultiCAN Node 0 Receiver Input Output of Capture/Compare channel 0 External Interrupt Input 3/T2CCU Capture/Compare Channel 0 Data Line 0 Input/Output MultiCAN Node 0 Transmitter Output Output of Capture/Compare channel 0 External Interrupt Input 4/T2CCU Capture/Compare Channel 1 Data Line 1 Input/Output External Interrupt Input 6 Timer 21 Input Data Line 2 Input/Output Timer 2 External Trigger Input Timer 21 External Flag Output Output of Capture/Compare channel 3 Data Line 3 Input/Output Symbol Pin Number (LQFP-64 / VQFN-48) P4 P4.3 40/31 Hi-Z CCPOS0_3 CCU6 Hall Input 0 T0_0 Timer 0 Input CC61_4 Output of Capture/Compare channel 1 T2CC2_0/ External Interrupt Input 5/T2CCU EXINT5_1 Capture/Compare Channel 2 D4 Data Line 4 Input/Output Data Sheet 16 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State Hi-Z CCPOS1_3 CCU6 Hall Input 1 T1_0 Timer 1 Input COUT61_2 Output of Capture/Compare channel 1 T2CC3_0/ External Interrupt Input 6/T2CCU EXINT6_2 Capture/Compare Channel 3 D5 Data Line 5 Input/Output CCPOS2_3 CCU6 Hall Input 2 T2_0 Timer 2 Input CC62_2 Output of Capture/Compare channel 2 T2CC4_0 Compare Output Channel 4 D6 Data Line 6 Input/Output CTRAP_3 COUT62_2 T2CC5_0 D7 CCU6 Trap Input Output of Capture/Compare channel 2 Compare Output Channel 5 Data Line 7 Input/Output Symbol Pin Number (LQFP-64 / VQFN-48) P4.5 46/- P4.6 47/- Hi-Z P4.7 48/- Hi-Z Data Sheet 17 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State I/O Port 5 Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1, T2CCU, JTAG and External Interface. PU PU PU EXINT1_1 A0 EXINT2_1 A1 RXD_2 T2CC2_2/ EXINT5_3 A2 External Interrupt Input 1 Address Line 0 Output External Interrupt Input 2 Address Line 1 Output UART Receive Data Input External Interrupt Input 5/T2CCU Capture/Compare Channel 2 Address Line 2 Output Symbol Pin Number (LQFP-64 / VQFN-48) P5 P5.0 P5.1 P5.2 8/9/12/- P5.3 13/- PU CCPOS0_0 CCU6 Hall Input 0 EXINT1_0 External Interrupt Input 1 T12HR_2 CCU6 Timer 12 Hardware Run Input CC61_3 Input of Capture/Compare channel 1 TXD_2 UART Transmit Data Output/Clock Output T2CC5_2 Compare Output Channel 5 A3 Address Line 3 Output CCPOS1_0 CCU6 Hall Input 1 EXINT2_0 External Interrupt Input 2 T13HR_2 CCU6 Timer 13 Hardware Run Input CC62_3 Input of Capture/Compare channel 2 RXDO_2 UART Transmit Data Output T2CC4_2 Compare Output Channel 4 A4 Address Line 4 Output P5.4 14/- PU Data Sheet 18 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State PU CCPOS2_0 CCU6 Hall Input 2 CTRAP_1 CCU6 Trap Input CC60_3 Input of Capture/Compare channel 0 TDO_1 JTAG Serial Data Output TXD1_2 UART1 Transmit Data Output/ Clock Output T2CC0_2/ External Interrupt Input 3/T2CCU EXINT3_3 Capture/Compare Channel 0 A5 Address Line 5 Output TCK_1 RXDO1_2 T2CC1_2/ EXINT4_3 A6 TDI_1 RXD1_2 T2CC3_2/ EXINT6_4 A7 JTAG Clock Input UART1 Transmit Data Output External Interrupt Input 4/T2CCU Capture/Compare Channel 1 Address Line 6 Output JTAG Serial Data Input UART1 Receive Data Input External Interrupt Input 6/T2CCU Capture/Compare Channel 3 Address Line 7 Output Symbol Pin Number (LQFP-64 / VQFN-48) P5.5 15/- P5.6 19/- PU P5.7 20/- PU Data Sheet 19 V1.5, 2011-03 XC87xCLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Type Reset Function State - - I/O Port Supply (3.3 or 5.0 V) Also used by EVR and analog modules. All pins must be connected. I/O Ground All pins must be connected. Core Supply Monitor (2.5 V) Core Supply Ground ADC Reference Voltage ADC Reference Ground Analog Input 0 Analog Input 1 Analog Input 2 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7 External Oscillator Input (Feedback resistor required, normally NC) External Oscillator Output (Feedback resistor required, normally NC) JTAG Test Mode Select Reset Input Monitor & BootStrap Loader Control Test Mode (External pull down device required) No Connection Symbol Pin Number (LQFP-64 / VQFN-48) VDDP VSSP VDDC VSSC VAREF VAGND AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 XTAL1 XTAL2 TMS MBC TM NC 7, 25, 55/ 17, 41 26, 54/ 18, 40 6/8 5/7 32/23 31/22 22/23/15 24/16 27/28/19 29/20 30/21 33/24 4/6 3/5 16/11 58/44 57/43 56/42 - - - - - I I I I I I I I I O I I I - - - - - - - Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z PD PU PU - - RESET 53/39 Data Sheet 20 V1.5, 2011-03 XC87xCLM Functional Description 3 Functional Description Chapter 3 provides an overview of the XC87x functional description. 3.1 Processor Architecture The XC87x is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC87x CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The XC87x CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and Special Function Registers (SFRs). Figure 6 shows the CPU functional blocks. Internal Data Memory Core SFRs External Data Memory 16-bit Registers & Memory Interface Program Memory Register Interface External SFRs ALU Opcode & Immediate Registers Multiplier / Divider Opcode Decoder Timer 0 / Timer 1 fCCLK Memory Wait Reset State Machine & Power Saving UART Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt Interrupt Controller Figure 6 CPU Block Diagram Data Sheet 21 V1.5, 2011-03 XC87xCLM Functional Description 3.2 * * * * * Memory Organization The XC87x CPU operates in the following address spaces: 8 Kbytes of Boot ROM program memory 256 bytes of internal RAM data memory 3 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory) A 128-byte Special Function Register area 64/52 Kbytes of Flash program memory (Flash devices) Figure 7 and Figure 8 illustrate the memory address spaces of the XC87x with 64Kbytes and 52Kbytes embedded Flash respectively. F' FFFF H Bank F Reserved F' 0000H E' FFFFH E' 0000H D' FFFFH D' 0000H C' FFFFH C' 0000H B' FFFFH B' 0000H A' FFFFH A' 0000H 9' FFFFH 9' 0000H 8' FFFFH 8' 0000H 7' FFFFH 7' 0000H 6' FFFFH 6' 0000H 5' FFFFH 5' 0000H 4' FFFFH 4' 0000H 3' FFFFH 3' 0000H 2' FFFFH 2' FEC0H 2' FE00H 2' FC00H 2' F000H 2' E000H 2' C000H 2' 0000H 1' FFFFH 1' 0000H 0' FFFFH 0' F000H External XRAM 3 KByte F' FFFF H F' FC00H F' F000H F' 0000H E' FFFFH E' 0000H D' FFFFH D' 0000H C' FFFFH C' 0000H B' FFFFH B' 0000H A' FFFFH A' 0000H 9' FFFFH 9' 0000H 8' FFFFH 8' 0000H 7' FFFFH 7' 0000H 6' FFFFH 6' 0000H 5' FFFFH 5' 0000H 4' FFFFH 4' 0000H 3' FFFFH 3' 0000H 2' FFFFH 2' FEC0H 2' FE00H 2' FC00H 2' F000H 2' E000H 2' C000H 2' 0000H 1' FFFFH 1' 0000H 0' FFFFH Bank E Bank D Bank C Bank B Bank A Bank 9 Bank 8 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 External Reserved External XRAM 3 KByte Reserved Boot ROM 8 KByte Reserved Bank 1 D-Flash 4 KByte Bank 0 Bank 2 Reserved External Reserved External Reserved External Reserved Memory Extension Stack Pointer (MEXSP) Indirect Address Direct Address FFH External Extension Stack RAM Internal RAM Special Function Registers 80H Reserved Internal RAM 7FH P-Flash 60 KByte 0' 0000H 0' 0000H 00H Code Space Data Space Internal Data Space Memory Map User Mode Figure 7 Memory Map of XC87x with 64K Flash Memory in user mode Data Sheet 22 V1.5, 2011-03 XC87xCLM Functional Description F'FFFF H F'FFFF H Reserved 1'0000H FFFF H FEC0H FE00H FC00H F000 H E000H External 1'0000H FFFF H FEC0H FE00H FC00H F000 H External Reserved External XRAM 2 KByte D-Flash 4 KByte External Reserved External XRAM 2 KByte Reserved Boot ROM 8 KByte C000H C000H P-Flash 48 KByte / Reserved 8000H Reserved / External 8000H Memory Extension Stack Pointer (MEXSP) P-Flash 32 KByte Reserved Extension Stack RAM Indirect Address Direct Address FF H Internal RAM Special Function Registers 80H 7FH Internal RAM 0000H 0000H 00 H Code Space Data Space Internal Data Space Memory Map User Mode Figure 8 Memory Map of XC87x with 52K Flash Memory in user mode Data Sheet 23 V1.5, 2011-03 XC87xCLM Functional Description 3.2.1 * * * Memory Protection Strategy The XC87x memory protection strategy includes: Basic protection: The user is able to block any external access via the boot option to any memory Read-out protection: The user is able to protect the contents in the Flash Flash program and erase protection These protection strategies are enabled by programming a valid password (16-bit nonone value) via Bootstrap Loader (BSL) mode 6. 3.2.1.1 Flash Memory Protection As long as a valid password is available, all external access to the device, including the Flash, will be blocked. For additional security, the Flash hardware protection can be enabled to implement a second layer of read-out protection, as well as to enable program and erase protection. Flash hardware protection is available only for Flash devices and comes in two modes: * * Mode 0: Only the P-Flash is protected; the D-Flash is unprotected Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 4. Table 4 Flash Protection Hardware Protection Mode Activation Selection P-Flash contents can be read by Flash Protection Modes Without hardware protection With hardware protection 0 1 Program a valid password via BSL mode 6 Bit 13 of password = 0 Read instructions in any program memory Bit 13 of password = 1 Bit 13 of password = 1 MSB of password = 0 MSB of password = 1 Read instructions in the P-Flash Read instructions in the P-Flash or DFlash Not possible External Not possible access to PFlash Not possible Data Sheet 24 V1.5, 2011-03 XC87xCLM Functional Description Table 4 Flash Protection P-Flash program and erase D-Flash contents can be read by Flash Protection Modes (cont'd) Without hardware protection Possible With hardware protection Possible only on the Possible only on the condition that MSB - 1 condition that MSB - 1 of password is set to 1 of password is set to 1 Read instructions in any program memory Read instructions in the P-Flash or DFlash Not possible Read instructions in any program memory External Not possible access to DFlash D-Flash program D-Flash erase Possible Not possible Possible Possible, on the condition that MSB - 1 of password is set to 1 Possible Possible, on these Possible, on the conditions: condition that MSB - 1 * MISC_CON.DFLASH of password is set to 1 EN bit is set to 1 prior to each erase operation; or * the MSB - 1 of password is set to 1 BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. To disable the flash protection, a password match is required. A password match triggers an automatic erase of the protected P-Flash and D-Flash contents, including the programmed password. With a valid password, the Flash hardware protection is then enabled or disabled upon next reset. For the other protection strategies, no reset is necessary. Although no protection scheme can be considered infallible, the XC87x memory protection strategy provides a very high level of protection for a general purpose microcontroller. Note: If ROM read-out protection is enabled, only read instructions in the ROM memory can target the ROM contents. Data Sheet 25 V1.5, 2011-03 XC87xCLM Functional Description 3.2.2 Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include: * * Mapping Paging 3.2.2.1 Address Extension by Mapping Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 9. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software. Data Sheet 26 V1.5, 2011-03 XC87xCLM Functional Description Standard Area (RMAP = 0) FF H Module 1 SFRs SYSCON0.RMAP rw Module 2 SFRs Module n SFRs ...... SFR Data (to/from CPU) 80 H Mapped Area (RMAP = 1) FF H Module (n+1) SFRs Module (n+2) SFRs Module m SFRs ...... 80 H Direct Internal Data Memory Address Figure 9 Address Extension by Mapping Data Sheet 27 V1.5, 2011-03 XC87xCLM Functional Description SYSCON0 System Control Register 0 7 6 0 r 5 4 IMODE rw 3 0 r 2 1 r Reset Value: 04H 1 0 r 0 RMAP rw Field RMAP Bits 0 Type Description rw Interrupt Node XINTR0 Enable 0 The access to the standard SFR area is enabled 1 The access to the mapped SFR area is enabled Reserved Returns 1 if read; should be written with 1. Reserved Returns 0 if read; should be written with 0. 1 0 2 [7:5], 3,1 r r Note: The RMAP bit should be cleared/set by ANL or ORL instructions.The rest bits of SYSCON0 should not be modified. 3.2.2.2 Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the XC87x has a 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 10. Data Sheet 28 V1.5, 2011-03 XC87xCLM Functional Description SFR Address (from CPU) MOD_PAGE.PAGE rw PAGE 0 SFR0 SFR1 SFRx ...... PAGE 1 SFR0 SFR Data (to/from CPU) SFR1 SFRy ...... ...... PAGE q SFR0 SFR1 SFRz ...... Module Figure 10 Address Extension by Paging In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can: * Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or 29 V1.5, 2011-03 Data Sheet XC87xCLM Functional Description * Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred) ST3 ST2 ST1 ST0 STNR value update from CPU PAGE Figure 11 Storage Elements for Paging With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC87x supports local address extension for: * * * * Parallel Ports Analog-to-Digital Converter (ADC) Capture/Compare Unit 6 (CCU6) System Control Registers Data Sheet 30 V1.5, 2011-03 XC87xCLM Functional Description The page register has the following definition: MOD_PAGE Page Register for module MOD 7 OP w 6 5 STNR w 4 3 0 r 2 Reset Value: 00H 1 PAGE rw 0 Field PAGE Bits [2:0] Type Description rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. STNR [5:4] w Data Sheet 31 V1.5, 2011-03 XC87xCLM Functional Description Field OP Bits [7:6] Type Description w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. Reserved Returns 0 if read; should be written with 0. 0 3 r 3.2.3 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit field PASS closes access to writing of all protected bits. In both cases, the value of the bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can only be changed when bit field PASS is written with 11000B, for example, writing D0H to PASSWD register disables the bit protection scheme. Note that access is opened for maximum 32 CCLKs if the "close access" password is not written. If "open access" password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include the N- and KDivider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the powerdown and slow-down enable bits, PD and SD. Data Sheet 32 V1.5, 2011-03 XC87xCLM Functional Description 3.2.3.1 Password Register Reset Value: 07H 5 PASS w 4 3 2 PROTECT _S rh 1 MODE rw 0 PASSWD Password Register 7 6 Field MODE Bits [1:0] Type Description rw Bit Protection Scheme Control Bits 00 Scheme disabled - direct access to the protected bits is allowed. 11 Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to protected bits. (default) Others:Scheme Enabled. These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B; only then, will the MODE[1:0] be registered. Bit Protection Signal Status Bit This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected bits. Password Bits The Bit Protection Scheme only recognizes three patterns. 11000B Enables writing of the bit field MODE. 10011B Opens access to writing of all protected bits. 10101B Closes access to writing of all protected bits PROTECT_S 2 rh PASS [7:3] w Data Sheet 33 V1.5, 2011-03 XC87xCLM Functional Description 3.2.4 XC87x Register Overview The SFRs of the XC87x are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Chapter 3.2.4.1 to Chapter 3.2.4.15. Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.2.4.1 CPU Registers The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 5 RMAP = 0 or 1 81H 82H 83H 87H 88H 89H SP Reset: 07H Stack Pointer Register DPL Reset: 00H Data Pointer Register Low DPH Reset: 00H Data Pointer Register High PCON Reset: 00H Power Control Register TCON Reset: 00H Timer Control Register TMOD Reset: 00H Timer Mode Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 8AH 8BH 8CH 8DH 94H 95H 96H TL0 Reset: 00H Timer 0 Register Low TL1 Reset: 00H Timer 1 Register Low TH0 Reset: 00H Timer 0 Register High TH1 Reset: 00H Timer 1 Register High MEX1 Reset: 00H Memory Extension Register 1 Reset: 00H Memory Extension Register 2 MEX3 Reset: 00H Memory Extension Register 3 MEX2 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type MCM rw MCB1 9 rw 0 r CB r MCB rw MXB1 9 rw MXM rw DPL7 rw DPH7 rw SMOD rw TF1 rwh GATE 1 rw TR1 rw T1S rw DPL6 rw DPH6 rw DPL5 rw DPH5 rw 0 r TF0 rwh T1M rw VAL rwh VAL rwh VAL rwh VAL rwh NB rw IB rw MXB rw TR0 rw DPL4 rw DPH4 rw SP rw DPL3 rw DPH3 rw GF1 rw IE1 rwh GATE 0 rw DPL2 rw DPH2 rw GF0 rw IT1 rw T0S rw DPL1 rw DPH1 rw 0 r IE0 rwh T0M rw DPL0 rw DPH0 rw IDLE rw IT0 rw CPU Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name Data Sheet 34 V1.5, 2011-03 XC87xCLM Functional Description Table 5 97H CPU Register Overview (cont'd) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r EA rw 0 r 0 r CY rwh ACC7 rw ECCIP 3 rw B7 rw PCCIP 3 rw PCCIP 3H rw AC rwh ACC6 rw ECCIP 2 rw B6 rw PCCIP 2 rw PCCIP 2H rw 0 r ET2 rw PT2 rw PT2H rw F0 rw ACC5 rw ECCIP 1 rw B5 rw PCCIP 1 rw PCCIP 1H rw Addr Register Name MEXSP Reset: 7FH Memory Extension Stack Pointer Register SCON Reset: 00H Serial Channel Control Register SBUF Reset: 00H Serial Data Buffer Register EO Reset: 00H Extended Operation Register 7 0 r SM0 rw 6 5 4 3 MXSP rwh 2 1 0 98H 99H A2H SM1 rw SM2 rw REN rw VAL rwh TRAP_ EN rw ES rw PS rw PSH rw RS1 rw ACC4 rw ECCIP 0 rw B4 rw PCCIP 0 rw PCCIP 0H rw TB8 rw RB8 rwh TI rwh RI rwh 0 r ET1 rw PT1 rw PT1H rw RS0 rw ACC3 rw EXM rw B3 rw PXM rw PXMH rw EX1 rw PX1 rw PX1H rw OV rwh ACC2 rw EX2 rw B2 rw PX2 rw PX2H rw ET0 rw PT0 rw PT0H rw F1 rw ACC1 rw ESSC rw B1 rw PSSC rw PSSC H rw DPSE L0 rw EX0 rw PX0 rw PX0H rw P rh ACC0 rw EADC rw B0 rw PADC rw PADC H rw A8H B8H B9H D0H E0H E8H IEN0 Reset: 00H Interrupt Enable Register 0 IP Reset: 00H Interrupt Priority Register IPH Reset: 00H Interrupt Priority High Register PSW Reset: 00H Program Status Word Register ACC Reset: 00H Accumulator Register IEN1 Reset: 00H Interrupt Enable Register 1 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type F0H F8H B B Register Reset: 00H Bit Field Type Bit Field Type IP1 Reset: 00H Interrupt Priority 1 Register F9H IPH1 Reset: 00H Bit Field Interrupt Priority 1 High Register Type 3.2.4.2 MDU Registers The MDU SFRs can be accessed in the mapped memory area (RMAP = 1). Table 6 RMAP = 1 B0H MDUSTAT Reset: 00H MDU Status Register Bit Field Type 0 r BSY rh IERR rwh IRDY rwh MDU Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name Data Sheet 35 V1.5, 2011-03 XC87xCLM Functional Description Table 6 B1H MDU Register Overview (cont'd) Bit Bit Field Type Addr Register Name MDUCON Reset: 00H MDU Control Register 7 IE rw 6 IR rw 5 RSEL rw 4 STAR T rwh DATA rw DATA rh DATA rw DATA rh DATA rw DATA rh DATA rw DATA rh DATA rw DATA rh DATA rw DATA rh 3 2 1 0 OPCODE rw B2H B2H B3H B3H B4H B4H B5H B5H B6H B6H B7H B7H MD0 Reset: 00H MDU Operand Register 0 MR0 Reset: 00H MDU Result Register 0 MD1 Reset: 00H MDU Operand Register 1 MR1 Reset: 00H MDU Result Register 1 MD2 Reset: 00H MDU Operand Register 2 MR2 Reset: 00H MDU Result Register 2 MD3 Reset: 00H MDU Operand Register 3 MR3 Reset: 00H MDU Result Register 3 MD4 Reset: 00H MDU Operand Register 4 MR4 Reset: 00H MDU Result Register 4 MD5 Reset: 00H MDU Operand Register 5 MR5 Reset: 00H MDU Result Register 5 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 3.2.4.3 CORDIC Registers The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1). Table 7 RMAP = 1 9AH 9BH CD_CORDXL Reset: 00H CORDIC X Data Low Byte CD_CORDXH Reset: 00H CORDIC X Data High Byte Bit Field Type Bit Field Type DATAL rw DATAH rw CORDIC Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name Data Sheet 36 V1.5, 2011-03 XC87xCLM Functional Description Table 7 9CH 9DH 9EH 9FH A0H CORDIC Register Overview (cont'd) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type KEEP Z rw MPS rw KEEP Y rw KEEP X rw X_USI GN rw DMAP rw ST_M ODE rw Addr Register Name CD_CORDYL Reset: 00H CORDIC Y Data Low Byte CD_CORDYH Reset: 00H CORDIC Y Data High Byte CD_CORDZL Reset: 00H CORDIC Z Data Low Byte CD_CORDZH Reset: 00H CORDIC Z Data High Byte CD_STATC Reset: 00H CORDIC Status and Data Control Register CD_CON Reset: 00H CORDIC Control Register 7 6 5 4 DATAL rw DATAH rw DATAL rw DATAH rw 3 2 1 0 INT_E N rw ROTV EC rw EOC rwh ERRO R rh BSY rh ST rwh A1H MODE rw 3.2.4.4 System Control Registers The system control SFRs can be accessed in the mapped memory area (RMAP = 0). Table 8 RMAP = 0 or 1 8FH SYSCON0 Reset: 04H System Control Register 0 Bit Field Type RMAP = 0 BFH SCU_PAGE Page Register Reset: 00H Bit Field Type OP w STNR w 0 r PAGE rwh 0 r IMOD E rw 0 r 1 r 0 r RMAP rw SCU Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name RMAP = 0, PAGE 0 B3H MODPISEL Reset: 00H Peripheral Input Select Register Bit Field Type B4H IRCON0 Reset: 00H Interrupt Request Register 0 Bit Field 0 r 0 URRIS H rw EXINT 6 rwh CANS RC2 rwh 0 r JTAGT DIS rw EXINT 5 rwh CANS RC1 rwh JTAGT CKS rw EXINT 4 rwh ADCS R1 rwh CANS RC3 rwh EXINT 2IS rw EXINT 3 rwh ADCS R0 rwh EXINT 1IS rw EXINT 2 rwh RIR rwh 0 r EXINT 0IS rw EXINT 1 rwh TIR rwh URRIS rw EXINT 0 rwh EIR rwh CANS RC0 rwh Type B5H IRCON1 Reset: 00H Interrupt Request Register 1 Bit Field Type B6H IRCON2 Reset: 00H Interrupt Request Register 2 Bit Field Type r 0 r Data Sheet 37 V1.5, 2011-03 XC87xCLM Functional Description Table 8 B7H SCU Register Overview (cont'd) Bit Bit Field Type Bit Field Type Bit Field Type 0 r 0 r Addr Register Name EXICON0 Reset: F0H External Interrupt Control Register 0 EXICON1 Reset: 3FH External Interrupt Control Register 1 NMICON Reset: 00H NMI Control Register 7 EXINT3 rw 0 r 6 5 EXINT2 rw EXINT6 rw 4 3 EXINT1 rw EXINT5 rw 2 1 EXINT0 rw EXINT4 rw NMI PLL rw FNMI PLL rwh 0 BAH BBH NMI ECC rw FNMI ECC rwh BGSEL rw NMI VDDP rw FNMI VDDP rwh NDOV EN rw 0 r 0 r BRDIS rw NMI OCDS rw FNMI OCDS rwh NMI FLASH rw FNMI FLASH rwh BRPRE rw NMI WDT rw FNMI WDT rwh R rw BCH NMISR Reset: 00H NMI Status Register Bit Field Type BDH BCON Reset: 20H Baud Rate Control Register Bit Field Type BEH BG Reset: 00H Baud Rate Timer/Reload Register FDCON Reset: 00H Fractional Divider Control Register FDSTEP Reset: 00H Fractional Divider Reload Register FDRES Reset: 00H Fractional Divider Result Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type BGS rw SYNE N rw ERRS YN rwh BR_VALUE rwh EOFS YN rwh STEP rw RESULT rh BRK rwh NDOV rwh FDM rw FDEN rw E9H EAH EBH RMAP = 0, PAGE 1 B3H B4H ID Identity Register Reset: 49H Bit Field Type Bit Field Type B5H PMCON1 Reset: 00H Power Mode Control Register 1 Bit Field Type B6H OSC_CON Reset: XXH OSC Control Register Bit Field Type B7H PLL_CON Reset: 18H PLL Control Register Bit Field Type BAH CMCON Reset: 10H Clock Control Register Bit Field Type KDIV rw 0 r VDDP WARN rh 0 r PLLRD RES rwh WDT RST rwh CDC_ DIS rw PLLBY P rwh PRODID r WKRS rwh CAN_ DIS rw PLLPD rw NDIV rw FCCF G rw WK SEL rw MDU_ DIS rw 0 r SD rw T2CC U_DIS rw XPD rw PD rwh CCU_ DIS rw OSC SS rwh SSC_ DIS rw EORD RES rwh PLLR rh CLKREL rw VERID r WS rw ADC_ DIS rw EXTO SCR rh PLL_L OCK rh PMCON0 Reset: 80H Power Mode Control Register 0 Data Sheet 38 V1.5, 2011-03 XC87xCLM Functional Description Table 8 BBH SCU Register Overview (cont'd) Bit Bit Field Type Addr Register Name PASSWD Reset: 07H Password Register 7 6 5 PASS w 4 3 2 PROT ECT_S rh 1 MODE rw 0 BEH E9H COCON Reset: 00H Clock Output Control Register MISC_CON Reset: 00H Miscellaneous Control Register Bit Field Type Bit Field COUTS rw ADCE TR0_ MUX rw ADCE TR1_ MUX rw NDIV rw CCCF G rw MDUC CFG rw TLEN rw 0 r 0 COREL rw DFLAS HEN rwh PDIV rw Type EAH EBH PLL_CON1 Reset: 20H PLL Control Register 1 CR_MISC Reset: 00H or 01H Reset Status Register Bit Field Type Bit Field Type RMAP = 0, PAGE 3 B3H XADDRH Reset: F0H On-chip XRAM Address Higher Order IRCON3 Reset: 00H Interrupt Request Register 3 Bit Field Type Bit Field Type B5H IRCON4 Reset: 00H Interrupt Request Register 4 Bit Field Type B6H MODIEN Reset: 07H Peripheral Interrupt Enable Register MODPISEL1 Reset: 00H Peripheral Input Select Register 1 MODPISEL2 Reset: 00H Peripheral Input Select Register 2 PMCON2 Reset: 00H Power Mode Control Register 2 Bit Field Type Bit Field Type Bit Field Type Bit Field Type BDH MODSUSP Reset: 01H Module Suspend Control Register MODPISEL3 Reset: 00H Peripheral Input Select Register 3 MODPISEL4 Reset: 00H Peripheral Input Select Register 4 Bit Field Type Bit Field Type Bit Field Type r CCUC CFG rw T2CCF G rw 0 r HDRS T rwh ADDRH rw 0 r 0 r 0 r EXINT6IS rw 0 r 0 r 0 r 0 r 0 r CCTS USP rw CIS rw EXINT5IS rw T21SU SP rw T2SUS P rw SIS rw EXINT4IS rw T13SU SP rw T2EXI S rw CANS RC5 rwh CANS RC7 rwh CCU6 SR1 rwh CCU6 SR3 rwh CM5E N rw CM4E N rw 0 r 0 r RIREN rw T21EX IS rw T21IS rw T2IS rw T1IS rw UART 1_DIS rw T12SU SP rw MIS rw EXINT3IS rw CANS RC4 rwh CANS RC6 rwh TIREN rw 0 r T0IS rw T21_D IS rw WDTS USP rw CCU6 SR0 rwh CCU6 SR2 rwh EIREN rw B4H B7H UR1RIS rw BAH BBH BEH EAH Data Sheet 39 V1.5, 2011-03 XC87xCLM Functional Description 3.2.4.5 WDT Registers The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Table 9 RMAP = 1 BBH WDTCON Reset: 00H Watchdog Timer Control Register WDTREL Reset: 00H Watchdog Timer Reload Register WDTWINB Reset: 00H Watchdog Window-Boundary Count Register WDTL Reset: 00H Watchdog Timer Register Low WDTH Reset: 00H Watchdog Timer Register High Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r WINB EN rw WDTP R rh 0 r WDTE N rw WDTR S rwh WDTI N rw WDT Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name BCH WDTREL rw WDTWINB rw WDT rh WDT rh BDH BEH BFH 3.2.4.6 Port Registers The Port SFRs can be accessed in the standard memory area (RMAP = 0). Table 10 RMAP = 0 B2H PORT_PAGE Page Register Reset: 00H Bit Field Type OP w STNR w 0 r PAGE rwh Port Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name RMAP = 0, PAGE 0 80H 86H 90H 91H 92H 93H P0_DATA Reset: 00H P0 Data Register P0_DIR Reset: 00H P0 Direction Register P1_DATA Reset: 00H P1 Data Register P1_DIR Reset: 00H P1 Direction Register P5_DATA Reset: 00H P5 Data Register P5_DIR Reset: 00H P5 Direction Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type P7 rwh P7 rw P7 rwh P7 rw P7 rwh P7 rw P6 rwh P6 rw P6 rwh P6 rw P6 rwh P6 rw P5 rwh P5 rw P5 rwh P5 rw P5 rwh P5 rw P4 rwh P4 rw P4 rwh P4 rw P4 rwh P4 rw P3 rwh P3 rw P3 rwh P3 rw P3 rwh P3 rw P2 rwh P2 rw P2 rwh P2 rw P2 rwh P2 rw P1 rwh P1 rw P1 rwh P1 rw P1 rwh P1 rw P0 rwh P0 rw P0 rwh P0 rw P0 rwh P0 rw Data Sheet 40 V1.5, 2011-03 XC87xCLM Functional Description Table 10 B0H B1H C8H C9H Port Register Overview (cont'd) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Addr Register Name P3_DATA Reset: 00H P3 Data Register P3_DIR Reset: 00H P3 Direction Register P4_DATA Reset: 00H P4 Data Register P4_DIR Reset: 00H P4 Direction Register 7 P7 rwh P7 rw P7 rwh P7 rw 6 P6 rwh P6 rw P6 rwh P6 rw 5 P5 rwh P5 rw P5 rwh P5 rw 4 P4 rwh P4 rw P4 rwh P4 rw 3 P3 rwh P3 rw P3 rwh P3 rw 2 P2 rwh P2 rw P2 rwh P2 rw 1 P1 rwh P1 rw P1 rwh P1 rw 0 P0 rwh P0 rw P0 rwh P0 rw RMAP = 0, PAGE 1 80H P0_PUDSEL Reset: FFH P0 Pull-Up/Pull-Down Select Register P0_PUDEN Reset: C4H P0 Pull-Up/Pull-Down Enable Register P1_PUDSEL Reset: FFH P1 Pull-Up/Pull-Down Select Register P1_PUDEN Reset: FFH P1 Pull-Up/Pull-Down Enable Register P5_PUDSEL Reset: FFH P5 Pull-Up/Pull-Down Select Register P5_PUDEN Reset: FFH P5 Pull-Up/Pull-Down Enable Register P3_PUDSEL Reset: BFH P3 Pull-Up/Pull-Down Select Register P3_PUDEN Reset: 40H P3 Pull-Up/Pull-Down Enable Register P4_PUDSEL Reset: FFH P4 Pull-Up/Pull-Down Select Register P4_PUDEN Reset: 04H P4 Pull-Up/Pull-Down Enable Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw 86H 90H 91H 92H 93H B0H B1H C8H C9H RMAP = 0, PAGE 2 80H 86H 90H P0_ALTSEL0 Reset: 00H P0 Alternate Select 0 Register P0_ALTSEL1 Reset: 00H P0 Alternate Select 1 Register P1_ALTSEL0 Reset: 00H P1 Alternate Select 0 Register Bit Field Type Bit Field Type Bit Field Type P7 rw P7 rw P7 rw P6 rw P6 rw P6 rw P5 rw P5 rw P5 rw P4 rw P4 rw P4 rw P3 rw P3 rw P3 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw Data Sheet 41 V1.5, 2011-03 XC87xCLM Functional Description Table 10 91H 92H 93H B0H B1H C8H C9H Port Register Overview (cont'd) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Addr Register Name P1_ALTSEL1 Reset: 00H P1 Alternate Select 1 Register P5_ALTSEL0 Reset: 00H P5 Alternate Select 0 Register P5_ALTSEL1 Reset: 00H P5 Alternate Select 1 Register P3_ALTSEL0 Reset: 00H P3 Alternate Select 0 Register P3_ALTSEL1 Reset: 00H P3 Alternate Select 1 Register P4_ALTSEL0 Reset: 00H P4 Alternate Select 0 Register P4_ALTSEL1 Reset: 00H P4 Alternate Select 1 Register 7 P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw 6 P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw 5 P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw 4 P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw 3 P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw 2 P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw 1 P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw 0 P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw RMAP = 0, PAGE 3 80H 86H P0_OD Reset: 00H P0 Open Drain Control Register P0_DS Reset: FFH P0 Drive Strength Control Register P1_OD Reset: 00H P1 Open Drain Control Register P1_DS Reset: FFH P1 Drive Strength Control Register P5_OD Reset: 00H P5 Open Drain Control Register P5_DS Reset: FFH P5 Drive Strength Control Register P3_OD Reset: 00H P3 Open Drain Control Register P3_DS Reset: FFH P3 Drive Strength Control Register P4_OD Reset: 00H P4 Open Drain Control Register P4_DS Reset: FFH P4 Drive Strength Control Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw 90H 91H 92H 93H B0H B1H C8H C9H Data Sheet 42 V1.5, 2011-03 XC87xCLM Functional Description 3.2.4.7 ADC Registers The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 RMAP = 0 D1H ADC_PAGE Page Register Reset: 00H Bit Field Type OP w STNR w 0 r PAGE rw ADC Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name RMAP = 0, PAGE 0 CAH CBH ADC_GLOBCTR Reset: 30H Global Control Register ADC_GLOBSTR Reset: 00H Global Status Register Bit Field Type Bit Field Type CCH ADC_PRAR Reset: 00H Priority and Arbitration Register Bit Field Type CDH CEH CFH ADC_LCBR Reset: B7H Limit Check Boundary Register ADC_INPCR0 Reset: 00H Input Class 0 Register ADC_ETRCR Reset: 00H External Trigger Control Register Bit Field Type Bit Field Type Bit Field Type SYNE N1 rw SYNE N0 rw ASEN 1 rw ANON rw 0 r ASEN 0 rw 0 r DW rw CTC rw CHNR rh ARBM rw CSM1 rw 0 r PRIO1 rw 0 r SAMP LE rh CSM0 rw BUSY rh PRIO0 rw BOUND1 rw STC rw ETRSEL1 rw BOUND0 rw ETRSEL0 rw RMAP = 0, PAGE 1 CAH CBH CCH CDH CEH CFH D2H D3H ADC_CHCTR0 Reset: 00H Channel Control Register 0 ADC_CHCTR1 Reset: 00H Channel Control Register 1 ADC_CHCTR2 Reset: 00H Channel Control Register 2 ADC_CHCTR3 Reset: 00H Channel Control Register 3 ADC_CHCTR4 Reset: 00H Channel Control Register 4 ADC_CHCTR5 Reset: 00H Channel Control Register 5 ADC_CHCTR6 Reset: 00H Channel Control Register 6 ADC_CHCTR7 Reset: 00H Channel Control Register 7 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw Data Sheet 43 V1.5, 2011-03 XC87xCLM Functional Description Table 11 RMAP = 0, PAGE 2 CAH CBH CCH CDH CEH CFH D2H D3H ADC_RESR0L Reset: 00H Result Register 0 Low ADC_RESR0H Reset: 00H Result Register 0 High ADC_RESR1L Reset: 00H Result Register 1 Low ADC_RESR1H Reset: 00H Result Register 1 High ADC_RESR2L Reset: 00H Result Register 2 Low ADC_RESR2H Reset: 00H Result Register 2 High ADC_RESR3L Reset: 00H Result Register 3 Low ADC_RESR3H Reset: 00H Result Register 3 High Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type RESULT rh 0 r VF rh RESULT rh 0 r VF rh RESULT rh 0 r VF rh RESULT rh 0 r VF rh DRC rh CHNR rh ADC Register Overview (cont'd) Bit 7 6 5 4 3 2 1 0 Addr Register Name RESULT rh DRC rh CHNR rh RESULT rh DRC rh CHNR rh RESULT rh DRC rh CHNR rh RESULT rh RMAP = 0, PAGE 3 CAH CBH CCH CDH CEH CFH D2H D3H ADC_RESRA0L Reset: 00H Result Register 0, View A Low ADC_RESRA0H Reset: 00H Result Register 0, View A High ADC_RESRA1L Reset: 00H Result Register 1, View A Low ADC_RESRA1H Reset: 00H Result Register 1, View A High ADC_RESRA2L Reset: 00H Result Register 2, View A Low ADC_RESRA2H Reset: 00H Result Register 2, View A High ADC_RESRA3L Reset: 00H Result Register 3, View A Low ADC_RESRA3H Reset: 00H Result Register 3, View A High Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type RESULT rh VF rh RESULT rh VF rh RESULT rh VF rh RESULT rh VF rh DRC rh CHNR rh RESULT rh DRC rh CHNR rh RESULT rh DRC rh CHNR rh RESULT rh DRC rh CHNR rh RESULT rh RMAP = 0, PAGE 4 CAH ADC_RCR0 Reset: 00H Result Control Register 0 Bit Field Type VFCT R rw WFR rw 0 r IEN rw 0 r DRCT R rw Data Sheet 44 V1.5, 2011-03 XC87xCLM Functional Description Table 11 CBH ADC Register Overview (cont'd) Bit Bit Field Type Addr Register Name ADC_RCR1 Reset: 00H Result Control Register 1 7 VFCT R rw VFCT R rw VFCT R rw 6 WFR rw WFR rw WFR rw 0 r 5 0 r 0 r 0 r 4 IEN rw IEN rw IEN rw 3 2 0 r 0 r 0 r 1 0 DRCT R rw DRCT R rw DRCT R rw CCH ADC_RCR2 Reset: 00H Result Control Register 2 Bit Field Type CDH ADC_RCR3 Reset: 00H Result Control Register 3 Bit Field Type CEH ADC_VFCR Reset: 00H Valid Flag Clear Register Bit Field Type VFC3 w VFC2 w VFC1 w VFC0 w RMAP = 0, PAGE 5 CAH ADC_CHINFR Reset: 00H Channel Interrupt Flag Register Bit Field Type CBH ADC_CHINCR Reset: 00H Channel Interrupt Clear Register Bit Field Type CCH ADC_CHINSR Reset: 00H Channel Interrupt Set Register Bit Field Type CDH ADC_CHINPR Reset: 00H Channel Interrupt Node Pointer Register ADC_EVINFR Reset: 00H Event Interrupt Flag Register Bit Field Type Bit Field Type CFH ADC_EVINCR Reset: 00H Event Interrupt Clear Flag Register Bit Field Type CHINF 7 rh CHINC 7 w CHINS 7 w CHINP 7 rw EVINF 7 rh EVINC 7 w EVINS 7 w EVINP 7 rw CHINF 6 rh CHINC 6 w CHINS 6 w CHINP 6 rw EVINF 6 rh EVINC 6 w EVINS 6 w EVINP 6 rw CHINF 5 rh CHINC 5 w CHINS 5 w CHINP 5 rw EVINF 5 rh EVINC 5 w EVINS 5 w EVINP 5 rw CHINF 4 rh CHINC 4 w CHINS 4 w CHINP 4 rw EVINF 4 rh EVINC 4 w EVINS 4 w EVINP 4 rw CHINF 3 rh CHINC 3 w CHINS 3 w CHINP 3 rw 0 r 0 r 0 r 0 r CHINF 2 rh CHINC 2 w CHINS 2 w CHINP 2 rw CHINF 1 rh CHINC 1 w CHINS 1 w CHINP 1 rw EVINF 1 rh EVINC 1 w EVINS 1 w EVINP 1 rw CHINF 0 rh CHINC 0 w CHINS 0 w CHINP 0 rw EVINF 0 rh EVINC 0 w EVINS 0 w EVINP 0 rw CEH D2H ADC_EVINSR Reset: 00H Bit Field Event Interrupt Set Flag Register Type D3H ADC_EVINPR Reset: 00H Event Interrupt Node Pointer Register Bit Field Type RMAP = 0, PAGE 6 CAH ADC_CRCR1 Reset: 00H Conversion Request Control Register 1 ADC_CRPR1 Reset: 00H Conversion Request Pending Register 1 Bit Field Type Bit Field Type CH7 rwh CHP7 rwh CH6 rwh CHP6 rwh CH5 rwh CHP5 rwh CH4 rwh CHP4 rwh 0 r 0 r CBH Data Sheet 45 V1.5, 2011-03 XC87xCLM Functional Description Table 11 CCH ADC Register Overview (cont'd) Bit Bit Field Type Bit Field Type Addr Register Name ADC_CRMR1 Reset: 00H Conversion Request Mode Register 1 ADC_QMR0 Reset: 00H Queue Mode Register 0 7 Rsv r CEV w Rsv r EXTR rh EXTR rh EXTR w 6 LDEV w TREV w 0 r ENSI rh ENSI rh ENSI w 5 CLRP ND w FLUS H w EMPT Y rh RF rh RF rh RF w 4 SCAN rw CLRV w EV rh V rh V rh 0 r 3 ENSI rw 0 r 0 r 0 r 0 r 2 ENTR rw ENTR rw 1 0 r 0 r FILL rh REQCHNR rh REQCHNR rh REQCHNR w 0 ENGT rw ENGT rw CDH CEH ADC_QSR0 Reset: 20H Queue Status Register 0 Bit Field Type CFH D2H D2H ADC_Q0R0 Reset: 00H Queue 0 Register 0 ADC_QBUR0 Reset: 00H Queue Backup Register 0 ADC_QINR0 Reset: 00H Queue Input Register 0 Bit Field Type Bit Field Type Bit Field Type Data Sheet 46 V1.5, 2011-03 XC87xCLM Functional Description 3.2.4.8 Timer 2 Compare/Capture Unit Registers The Timer 2 Compare/Capture Unit SFRs can be accessed in the standard memory area (RMAP = 0). Table 12 RMAP = 0 C7H T2_PAGE Page Register Reset: 00H Bit Field Type OP w STNR w 0 r PAGE rwh T2CCU Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name RMAP = 0, PAGE 0 C0H T2_T2CON Reset: 00H Timer 2 Control Register Bit Field Type C1H T2_T2MOD Reset: 00H Timer 2 Mode Register Bit Field Type C2H T2_RC2L Reset: 00H Timer 2 Reload/Capture Register Low T2_RC2H Reset: 00H Timer 2 Reload/Capture Register High T2_T2L Reset: 00H Timer 2 Register Low T2_T2H Reset: 00H Timer 2 Register High T2_T2CON1 Reset: 03H Timer 2 Control Register 1 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type RMAP = 0, PAGE 1 C0H T2CCU_CCEN Reset: 00H T2CCU Capture/Compare Enable Register T2CCU_CCTBSELReset: 00H T2CCU Capture/Compare Time Base Select Register T2CCU_CCTRELLReset: 00H T2CCU Capture/Compare Timer Reload Register Low T2CCU_CCTRELHReset: 00H T2CCU Capture/Compare Timer Reload Register High T2CCU_CCTL Reset: 00H T2CCU Capture/Compare Timer Register Low Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type CASC rw CCM3 rw CCTT OV rwh CCTB 5 rw CCM2 rw CCTB 4 rw CCTB 3 rw CCM1 rw CCTB 2 rw CCTB 1 rw CCM0 rw CCTB 0 rw 0 r TF2 rwh T2RE GS rw EXF2 rwh T2RH EN rw EDGE SEL rw 0 r PREN rw RC2 rwh RC2 rwh THL2 rwh THL2 rwh TF2EN rw EXF2E N rw EXEN 2 rw TR2 rwh T2PRE rw C/T2 rw CP/ RL2 rw DCEN rw C3H C4H C5H C6H C1H C2H CCTREL rw CCTREL rw CCT rwh C3H C4H Data Sheet 47 V1.5, 2011-03 XC87xCLM Functional Description Table 12 C5H T2CCU Register Overview (cont'd) Bit Bit Field Type Bit Field Type CCTPRE rw Addr Register Name T2CCU_CCTH Reset: 00H T2CCU Capture/Compare Timer Register High T2CCU_CCTCON Reset: 00H T2CCU CaptureCcompare Timer Control Register 7 6 5 4 CCT rwh 3 2 1 0 C6H CCTO VF rwh CCTO VEN rw TIMSY N rw CCTS T rw RMAP = 0, PAGE 2 C0H T2CCU_COSHDWReset: 00H T2CCU Capture/compare Enable Register T2CCU_CC0L Reset: 00H T2CCU Capture/Compare Register 0 Low T2CCU_CC0H Reset: 00H T2CCU Capture/compare Register 0 High T2CCU_CC1L Reset: 00H T2CCU Capture/compare Register 1 Low T2CCU_CC1H Reset: 00H T2CCU Capture/compare Register 1 High T2CCU_CC2L Reset: 00H T2CCU Capture/compare Register 2 Low T2CCU_CC2H Reset: 00H T2CCU Capture/compare Register 2 High Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type ENSH DW rwh TXOV rwh COOU T5 rwh COOU T4 rwh COOU T3 rwh COOU T2 rwh COOU T1 rwh COOU T0 rwh C1H CCVALL rwh CCVALH rwh CCVALL rwh CCVALH rwh CCVALL rwh CCVALH rwh C2H C3H C4H C5H C6H RMAP = 0, PAGE 3 C0H T2CCU_COCON Reset: 00H T2CCU Compare Control Register T2CCU_CC3L Reset: 00H T2CCU Capture/compare Register 3 Low T2CCU_CC3H Reset: 00H T2CCU Capture/compare Register 3 High T2CCU_CC4L Reset: 00H T2CCU Capture/compare Register 4 Low T2CCU_CC4H Reset: 00H T2CCU Capture/compare Register 4 High T2CCU_CC5L Reset: 00H T2CCU Capture/compare Register 5 Low T2CCU_CC5H Reset: 00H T2CCU Capture/compare Register 5 High Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type CCM5 rw CCM4 rw CM5F rwh CM4F rwh POLB rw POLA rw COMOD rw C1H CCVALL rwh CCVALH rwh CCVALL rwh CCVALH rwh CCVALL rwh CCVALH rwh C2H C3H C4H C5H C6H Data Sheet 48 V1.5, 2011-03 XC87xCLM Functional Description Table 12 RMAP = 0, PAGE 4 C2H T2CCU_CCTDTCLReset: 00H T2CCU Capture/Compare Timer Dead-Time Control Register Low T2CCU_CCTDTCHReset: 00H T2CCU Capture/Compare Timer Dead-Time Control Register High Bit Field Type Bit Field Type DTRE S rwh DTR2 rh DTR1 rh DTR0 rh DTM rw DTLEV rw DTE2 rw DTE1 rw DTE0 rw T2CCU Register Overview (cont'd) Bit 7 6 5 4 3 2 1 0 Addr Register Name C3H 3.2.4.9 Timer 21 Registers The Timer 21 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 13 RMAP = 1 C0H T21_T2CON Reset: 00H Timer 2 Control Register Bit Field Type C1H T21_T2MOD Reset: 00H Timer 2 Mode Register Bit Field Type C2H T21_RC2L Reset: 00H Timer 2 Reload/Capture Register Low T21_RC2H Reset: 00H Timer 2 Reload/Capture Register High T21_T2L Reset: 00H Timer 2 Register Low T21_T2H Reset: 00H Timer 2 Register High T21_T2CON1 Reset: 03H Timer 2 Control Register 1 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r TF2 rwh T2RE GS rw EXF2 rwh T2RH EN rw EDGE SEL rw 0 r PREN rw RC2 rwh RC2 rwh THL2 rwh THL2 rwh TF2EN rw EXF2E N rw rw EXEN 2 rw TR2 rwh T2PRE rw rw C/T2 rw CP/ RL2 rw DCEN rw T21 Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name C3H C4H C5H C6H Data Sheet 49 V1.5, 2011-03 XC87xCLM Functional Description 3.2.4.10 CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 14 RMAP = 0 A3H CCU6_PAGE Page Register Reset: 00H Bit Field Type OP w STNR w 0 r PAGE rwh CCU6 Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name RMAP = 0, PAGE 0 9AH CCU6_CC63SRL Reset: 00H Capture/Compare Shadow Register for Channel CC63 Low CCU6_CC63SRH Reset: 00H Capture/Compare Shadow Register for Channel CC63 High CCU6_TCTR4L Reset: 00H Timer Control Register 4 Low Bit Field Type Bit Field Type Bit Field Type 9DH CCU6_TCTR4H Reset: 00H Timer Control Register 4 High Bit Field Type 9EH CCU6_MCMOUTSL Reset: 00H Multi-Channel Mode Output Shadow Register Low CCU6_MCMOUTSH Reset: 00H Multi-Channel Mode Output Shadow Register High CCU6_ISRL Reset: 00H Capture/Compare Interrupt Status Reset Register Low CCU6_ISRH Reset: 00H Capture/Compare Interrupt Status Reset Register High CCU6_CMPMODIFL Reset: 00H Compare State Modification Register Low CCU6_CMPMODIFH Reset: 00H Compare State Modification Register High CCU6_CC60SRL Reset: 00H Capture/Compare Shadow Register for Channel CC60 Low CCU6_CC60SRH Reset: 00H Capture/Compare Shadow Register for Channel CC60 High Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type T12 STD w T13 STD w STRM CM w STRH P w RT12 PM w RSTR w 0 r 0 r T12 STR w T13 STR w 0 r 0 r RT12 OM w RIDLE w MCC6 3S w MCC6 3R w RCC6 2F w RWH E w CURHS rw RCC6 2R w RCHE w 0 r 0 r CC60SL rwh CC60SH rwh RCC6 1F w 0 r RCC6 1R w RTRP F w MCC6 2S w MCC6 2R w 0 r 0 r CC63SL rw CC63SH rw DT RES w T12 RES w T13 RES w MCMPS rw EXPHS rw RCC6 0F w RT13 PM w MCC6 1S w MCC6 1R w RCC6 0R w RT13 CM w MCC6 0S w MCC6 0R w T12R S w T13R S w T12R R w T13R R w 9BH 9CH 9FH A4H A5H A6H A7H FAH FBH Data Sheet 50 V1.5, 2011-03 XC87xCLM Functional Description Table 14 FCH CCU6 Register Overview (cont'd) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Addr Register Name CCU6_CC61SRL Reset: 00H Capture/Compare Shadow Register for Channel CC61 Low CCU6_CC61SRH Reset: 00H Capture/Compare Shadow Register for Channel CC61 High CCU6_CC62SRL Reset: 00H Capture/Compare Shadow Register for Channel CC62 Low CCU6_CC62SRH Reset: 00H Capture/Compare Shadow Register for Channel CC62 High 7 6 5 4 rwh 3 2 1 0 CC61SL FDH CC61SH rwh CC62SL rwh CC62SH rwh FEH FFH RMAP = 0, PAGE 1 9AH CCU6_CC63RL Reset: 00H Capture/Compare Register for Channel CC63 Low CCU6_CC63RH Reset: 00H Capture/Compare Register for Channel CC63 High CCU6_T12PRL Reset: 00H Timer T12 Period Register Low CCU6_T12PRH Reset: 00H Timer T12 Period Register High CCU6_T13PRL Reset: 00H Timer T13 Period Register Low CCU6_T13PRH Reset: 00H Timer T13 Period Register High CCU6_T12DTCL Reset: 00H Dead-Time Control Register for Timer T12 Low CCU6_T12DTCH Reset: 00H Dead-Time Control Register for Timer T12 High CCU6_TCTR0L Reset: 00H Timer Control Register 0 Low Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type A7H CCU6_TCTR0H Reset: 00H Timer Control Register 0 High Bit Field Type FAH CCU6_CC60RL Reset: 00H Capture/Compare Register for Channel CC60 Low CCU6_CC60RH Reset: 00H Capture/Compare Register for Channel CC60 High CCU6_CC61RL Reset: 00H Capture/Compare Register for Channel CC61 Low Bit Field Type Bit Field Type Bit Field Type 0 r CTM rw 0 r DTR2 rh CDIR rh DTR1 rh STE1 2 rh STE1 3 rh DTR0 rh T12R rh T13R rh CC63VL rh CC63VH rh T12PVL rwh T12PVH rwh T13PVL rwh T13PVH rwh DTM rw 0 r T12 PRE rw T13 PRE rw DTE2 rw DTE1 rw T12CLK rw T13CLK rw DTE0 rw 9BH 9CH 9DH 9EH 9FH A4H A5H A6H CC60VL rh CC60VH rh CC61VL rh FBH FCH Data Sheet 51 V1.5, 2011-03 XC87xCLM Functional Description Table 14 FDH CCU6 Register Overview (cont'd) Bit Bit Field Type Bit Field Type Bit Field Type Addr Register Name CCU6_CC61RH Reset: 00H Capture/Compare Register for Channel CC61 High CCU6_CC62RL Reset: 00H Capture/Compare Register for Channel CC62 Low CCU6_CC62RH Reset: 00H Capture/Compare Register for Channel CC62 High 7 6 5 4 rh 3 2 1 0 CC61VH FEH CC62VL rh CC62VH rh FFH RMAP = 0, PAGE 2 9AH CCU6_T12MSELL Reset: 00H T12 Capture/Compare Mode Select Register Low CCU6_T12MSELH Reset: 00H T12 Capture/Compare Mode Select Register High CCU6_IENL Reset: 00H Capture/Compare Interrupt Enable Register Low Bit Field Type Bit Field Type Bit Field DBYP rw ENT1 2 PM rw EN STR rw ENT1 2 OM rw EN IDLE rw MSEL61 rw HSYNC rw ENCC 62F rw EN WHE rw ENCC 62R rw EN CHE rw ENCC 61F rw 0 r ENCC 61R rw EN TRPF rw MSEL60 rw MSEL62 rw ENCC 60F rw ENT1 3PM rw ENCC 60R rw ENT1 3CM rw 9BH 9CH Type 9DH CCU6_IENH Reset: 00H Capture/Compare Interrupt Enable Register High CCU6_INPL Reset: 40H Capture/Compare Interrupt Node Pointer Register Low CCU6_INPH Reset: 39H Capture/Compare Interrupt Node Pointer Register High CCU6_ISSL Reset: 00H Capture/Compare Interrupt Status Set Register Low CCU6_ISSH Reset: 00H Capture/Compare Interrupt Status Set Register High CCU6_PSLR Reset: 00H Passive State Level Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 9EH INPCHE rw 0 r ST12 PM w SSTR w PSL63 rwh 0 r 0 r T13TED rw 0 r MCM EN rw 0 r ST12 OM w SIDLE w 0 r INPCC62 rw INPT13 rw SCC6 2F w SWHE w SCC6 2R w SCHE w INPCC61 rw INPT12 rw SCC6 1F w SWH C w PSL rwh SCC6 1R w STRP F w INPCC60 rw INPERR rw SCC6 0F w ST13 PM w SCC6 0R w ST13 CM w 9FH A4H A5H A6H A7H FAH CCU6_MCMCTR Reset: 00H Bit Field Multi-Channel Mode Control Register Type CCU6_TCTR2L Reset: 00H Timer Control Register 2 Low Bit Field Type SWSYN rw 0 r T13TEC rw T13RSEL rw T12MODEN rw SWSEL rw T13 SSC rw T12 SSC rw FBH FCH CCU6_TCTR2H Reset: 00H Timer Control Register 2 High CCU6_MODCTRL Reset: 00H Modulation Control Register Low Bit Field Type Bit Field Type T12RSEL rw Data Sheet 52 V1.5, 2011-03 XC87xCLM Functional Description Table 14 FDH CCU6 Register Overview (cont'd) Bit Bit Field Type Addr Register Name CCU6_MODCTRH Reset: 00H Modulation Control Register High 7 ECT1 3O rw 6 0 r 5 4 3 2 1 0 T13MODEN rw 0 r TRPM 2 rw TRPEN rw TRPM 1 rw TRPM 0 rw FEH CCU6_TRPCTRL Reset: 00H Trap Control Register Low Bit Field Type FFH CCU6_TRPCTRH Reset: 00H Trap Control Register High Bit Field Type TRPP EN rw TRPE N13 rw RMAP = 0, PAGE 3 9AH CCU6_MCMOUTL Reset: 00H Multi-Channel Mode Output Register Low CCU6_MCMOUTH Reset: 00H Multi-Channel Mode Output Register High CCU6_ISL Reset: 00H Capture/Compare Interrupt Status Register Low CCU6_ISH Reset: 00H Capture/Compare Interrupt Status Register High CCU6_PISEL0L Reset: 00H Port Input Select Register 0 Low CCU6_PISEL0H Reset: 00H Port Input Select Register 0 High CCU6_PISEL2 Reset: 00H Port Input Select Register 2 CCU6_T12L Reset: 00H Timer T12 Counter Register Low CCU6_T12H Reset: 00H Timer T12 Counter Register High CCU6_T13L Reset: 00H Timer T13 Counter Register Low CCU6_T13H Reset: 00H Timer T13 Counter Register High CCU6_CMPSTATL Reset: 00H Compare State Register Low Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type FFH CCU6_CMPSTATH Reset: 00H Compare State Register High Bit Field Type 0 r T13IM rwh CC63 ST rh COUT 63PS rwh CC POS2 rh COUT 62PS rwh T12 PM rh STR rh ISTRP rw IST12HR rw 0 r 0 r T12 OM rh IDLE rh ICC62 F rh WHE rh R rh CURH rh ICC62 R rh CHE rh ICC61 F rh TRPS rh ICC61 R rh TRPF rh MCMP rh EXPH rh ICC60 F rh T13 PM rh ICC60 R rh T13 CM rh 9BH 9CH 9DH 9EH 9FH A4H FAH FBH FCH FDH FEH ISCC62 rw ISPOS2 rw 0 r T12CVL rwh T12CVH rwh T13CVL rwh T13CVH rwh CC POS1 rh CC62 PS rwh ISCC61 rw ISPOS1 rw ISCC60 rw ISPOS0 rw IST13HR rw CC POS0 rh COUT 61PS rwh CC62 ST rh CC61 PS rwh CC61 ST rh COUT 60PS rwh CC60 ST rh CC60 PS rwh Data Sheet 53 V1.5, 2011-03 XC87xCLM Functional Description 3.2.4.11 UART1 Registers The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 15 RMAP = 1 C8H C9H CAH CBH SCON Reset: 00H Serial Channel Control Register SBUF Reset: 00H Serial Data Buffer Register BCON Reset: 00H Baud Rate Control Register BG Reset: 00H Baud Rate Timer/Reload Register FDCON Reset: 00H Fractional Divider Control Register FDSTEP Reset: 00H Fractional Divider Reload Register FDRES Reset: 00H Fractional Divider Result Register SCON1 Reset: 07H Serial Channel Control Register 1 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r 0 r STEP rw RESULT rh NDOV EN rw TIEN rw RIEN rw 0 r BR_VALUE rwh NDOV rwh FDM rw FDEN rw SM0 rw SM1 rw SM2 rw REN rw VAL rwh BRPRE rw R rw TB8 rw RB8 rwh TI rwh RI rwh UART1 Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name CCH CDH CEH CFH 3.2.4.12 SSC Registers The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 16 RMAP = 0 A9H AAH SSC_PISEL Reset: 00H Port Input Select Register SSC_CONL Reset: 00H Control Register Low Programming Mode SSC_CONL Reset: 00H Control Register Low Operating Mode SSC_CONH Reset: 00H Control Register High Programming Mode Bit Field Type Bit Field Type Bit Field Type Bit Field Type EN rw MS rw LB rw PO rw 0 r 0 r AREN rw BEN rw PEN rw 0 r PH rw HB rw CIS rw BM rw BC rh REN rw TEN rw SIS rw MIS rw SSC Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name AAH ABH Data Sheet 54 V1.5, 2011-03 XC87xCLM Functional Description Table 16 ABH SSC Register Overview (cont'd) Bit Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Addr Register Name SSC_CONH Reset: 00H Control Register High Operating Mode SSC_TBL Reset: 00H Transmitter Buffer Register Low SSC_RBL Reset: 00H Receiver Buffer Register Low SSC_BRL Reset: 00H Baud Rate Timer Reload Register Low SSC_BRH Reset: 00H Baud Rate Timer Reload Register High 7 EN rw 6 MS rw 5 0 r 4 BSY rh 3 BE rwh 2 PE rwh 1 RE rwh 0 TE rwh ACH ADH AEH TB_VALUE rw RB_VALUE rh BR_VALUE rw BR_VALUE rw AFH 3.2.4.13 MultiCAN Registers The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0). Table 17 RMAP = 0 D8H ADCON Reset: 00H CAN Address/Data Control Register ADL Reset: 00H CAN Address Register Low ADH Reset: 00H CAN Address Register High DATA0 Reset: 00H CAN Data Register 0 DATA1 Reset: 00H CAN Data Register 1 DATA2 Reset: 00H CAN Data Register 2 DATA3 Reset: 00H CAN Data Register 3 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type V3 rw CA9 rwh V2 rw CA8 rwh 0 r CD rwh CD rwh CD rwh CD rwh V1 rw CA7 rwh V0 rw CA6 rwh CA5 rwh CA13 rwh AUAD rw CA4 rwh CA12 rwh BSY rh CA3 rwh CA11 rwh RWEN rw CA2 rwh CA10 rwh CAN Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name D9H DAH DBH DCH DDH DEH 3.2.4.14 OCDS Registers The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). Data Sheet 55 V1.5, 2011-03 XC87xCLM Functional Description Table 18 RMAP = 1 E9H MMCR2 Reset: 8UH Monitor Mode Control 2 Register MEXTCR Reset: 0UH Memory Extension Control Register MMWR1 Reset: 00H Monitor Work Register 1 MMWR2 Reset: 00H Monitor Work Register 2 MMCR Reset: 00H Monitor Mode Control Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type F2H MMSR Reset: 00H Monitor Mode Status Register Bit Field Type F3H MMBPCR Reset: 00H Breakpoints Control Register Bit Field Type F4H MMICR Reset: 00H Monitor Mode Interrupt Control Register MMDR Reset: 00H Monitor Mode Data Transfer Register Receive HWBPSR Reset: 00H Hardware Breakpoints Select Register HWBPDR Reset: 00H Hardware Breakpoints Data Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type 0 r BPSEL _P w HWBPxx rw MEXIT _P w MBCA M rw SWBC rw DVEC T rwh DRET R rwh MEXIT rwh MBCIN rwh 0 r EXBF rwh MSTE P rw SWBF rwh STMO DE rw EXBC rw 0 r MMWR1 rw MMWR2 rw MRAM S_P w HWB3 F rwh MRAM S rwh HWB2 F rwh HWB1 C rw MMUI E_P w MMRR rh BPSEL rw MMUI E rw RRIE_ P w TRF rh HWB1 F rwh RRF rh HWB0 F rwh DSUS P rw MBCO N rwh ALTDI rw MMEP rwh MMOD E rh JENA rh OCDS Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name EAH BANKBPx rw EBH ECH F1H HWB3C rw COMR ST rwh HWB2C rw MSTS EL rh HWB0C rw RRIE rw F5H F6H F7H Data Sheet 56 V1.5, 2011-03 XC87xCLM Functional Description 3.2.4.15 Flash Registers The Flash SFRs can be accessed in the mapped memory area (RMAP = 1). Table 19 RMAP = 1 D1H FCON Reset: 10H P-Flash Control Register Bit Field Type D2H EECON Reset: 10H D-Flash Control Register Bit Field Type D3H FCS Reset: 80H Flash Control and Status Register FEAL Reset: 00H Flash Error Address Register, Low Byte FEAH Reset: 00H Flash Error Address Register, High Byte FTVAL Reset: 78H Flash Timer Value Register FCS1 Reset: 00H Flash Control and Status Register 1 Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type MODE rw 0 r 0 r 0 r 1 r FBSY rh EEBS Y rh SBEIE rw YE rwh YE rwh FTEN rwh 1 r 1 r 0 r NVST R rw NVST R rw EEDE RR rwh MAS1 rw MAS1 rw EESE RR rwh ERAS E rw ERAS E rw FDER R rwh PROG rw PROG rw FSER R rwh Flash Register Overview Bit 7 6 5 4 3 2 1 0 Addr Register Name D4H ECCEADDR rh ECCEADDR rh OFVAL rw EEAB ORT rwh D5H D6H DDH Data Sheet 57 V1.5, 2011-03 XC87xCLM Functional Description 3.3 Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The pagination of the Flash memory allows each page to be erased independently. Features * * * * * * * * * * * * * * * In-System Programming (ISP) via UART In-Application Programming (IAP) Error Correction Code (ECC) for dynamic correction of single-bit errors Background program and erase operations for CPU load minimization Support for aborting erase operation Minimum program width of 1-byte for D-Flash and 2-bytes for P-Flash 1-page minimum erase width 1-byte read access Flash is delivered in erased state (read all ones) Operating supply voltage: 2.5 V 7.5 % Read access time: 1 x tCCLK = 38 ns1) Program time for 1 wordline: 1.6 ms2) Page erase time: 20 ms Mass erase time: 200 ms 1) Values shown here are typical values. fsys = 144 MHz 7.5% (fCCLK = 24 MHz 7.5 %) is the maximum frequency range for Flash read access. 2) Values shown here are typical values. fsys = 144 MHz 7.5% (fCCLK = 24 MHz 7.5 %) is the typical frequency range for Flash programming and erasing. fsysmin is used for obtaining the worst case timing. Data Sheet 58 V1.5, 2011-03 XC87xCLM Functional Description Table 20 and Table 21 shows the Flash data retention and endurance targets for Industrial profile and Automotive profile respectively. Table 20 Retention Program Flash 15 years Data Flash 15 years 10 years 5 years 1 year 1000 cycles 10,000 cycles 30,000 cycles 100,000 cycles 80,000 cycles 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes SAF and SAX variant SAK variant 1000 cycles up to 60 Kbytes Flash Data Retention and Endurance for Industrial Profile (Operating Conditions apply) Endurance1)2) Size Remarks 1) In Program Flash, one cycle refers to the programming of all pages in the flash bank and a mass erase. 2) In Data Flash, one cycle refers to the programming of all wordlines in a page and a page erase. Table 21 Retention Flash Data Retention and Endurance for Automotive Profile (Operating Conditions apply) Endurance1)2) 1000 cycles 1000 cycles 10,000 cycles 15,000 cycles 30,000 cycles 100,000 cycles Size up to 60 Kbytes 4 Kbytes 1 Kbytes 512 Bytes 256 Bytes 128 Bytes Remarks Program Flash 15 years Data Flash 15 years 5 years 2 years 2 years 1 year 1) In Program Flash, one cycle refers to the programming of all pages in the flash bank and a mass erase. 2) In Data Flash, one cycle refers to the programming of all wordlines in a page and a page erase. Data Sheet 59 V1.5, 2011-03 XC87xCLM Functional Description 3.3.1 Flash Bank Pagination The XC87x product family offers Flash devices with either 64 Kbytes or 52 Kbytes of embedded Flash memory. Each Flash device consists of a Program Flash (P-Flash) and a single Data Flash (D-Flash) bank. P-Flash has 120 pages of 8 wordlines per page with 64 bytes per wordline. D-Flash has 64 pages of 2 wordlines per page with 32 bytes per wordline. Both types can be used for code and data storage.. The label "Data" neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage. It is used to distinguish the different page width and wordline of each Flash bank. The internal structure of each Flash bank represents a page architecture for flexible erase capability. The minimum erase width is always a complete page. The D-Flash bank is divided into smaller size for extended erasing and reprogramming capability; even numbers for each page size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements. Data Sheet 60 V1.5, 2011-03 XC87xCLM Functional Description 3.4 Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC87x interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and determining the interrupt source. 3.4.1 Interrupt Source Figure 12 to Figure 16 give a general overview of the interrupt sources and nodes, and their corresponding control and status flags. WDT Overflow FNMIWDT NMIISR.0 NMIWDT NMICON.0 PLL Loss of Clock FNMIPLL NMIISR.1 NMIPLL NMICON.1 Flash Timer Overflow FNMIFLASH NMIISR.2 NMIFLASH NMICON.2 >=1 0073 H Non Maskable Interrupt VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIVDDP NMICON.5 Flash ECC Error FNMIECC NMIISR.6 NMIECC NMICON.6 Figure 12 Non-Maskable Interrupt Request Sources Data Sheet 61 V1.5, 2011-03 XC87xCLM Functional Description Highest Timer 0 Overflow TF0 TCON.5 ET0 IEN0.1 000B H IP.1/ IPH.1 Lowest Priority Level Timer 1 Overflow TF1 TCON.7 ET1 IEN0.3 001B H IP.3/ IPH.3 UART Receive UART Transmit RI SCON.0 TI SCON.1 >=1 ES IEN0.4 0023 H IP.4/ IPH.4 P o l l i n g S e q u e n c e EINT0 IT0 TCON.0 EXINT0 EXICON0.0/1 IE0 TCON.1 EX0 IEN0.0 0003 H IP.0/ IPH.0 IE1 EINT1 IT1 TCON.2 EXINT1 EXICON0.2/3 TCON.3 EX1 IEN0.2 0013 H IP.2/ IPH.2 EA IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 13 Interrupt Request Sources (Part 1) Data Sheet 62 V1.5, 2011-03 XC87xCLM Functional Description Timer 2 Overflow TF2 T2_T2CON.7 TF2EN T2_T2CON1.1 >=1 T2EX EXEN2 EDGES EL T2_T2MOD.5 T2_T2CON.3 EXF2 T2_T2CON.6 EXF2EN T2_T2CON1.0 Highest CCT Overflow CCTOVF T2CCU_CCTCON.3 CCTOVEN Lowest Priority Level T2CCU_CCTCON.2 >=1 Normal Divider Overflow NDOV FDCON.2 NDOVEN BCON.5 End of Syn Byte Syn Byte Error MultiCAN Node 0 EOFSYN FDCON.4 ERRSYN FDCON.5 SYNEN FDCON.6 ET2 IEN0.5 002B H IP.5/ IPH.5 CANSRC0 IRCON2.0 P o l l i n g S e q u e n c e ADC Service Request 0 ADC Service Request 1 MultiCAN Node 1 MultiCAN Node 2 ADCSRC0 IRCON1.3 ADCSRC1 IRCON1.4 >=1 EADC IEN1.0 0033 H IP1.0/ IPH1.0 CANSRC1 IRCON1.5 CANSRC2 IRCON1.6 Bitaddressable Request flag is cleared by hardware EA IEN0.7 Figure 14 Interrupt Request Sources (Part 2) Data Sheet 63 V1.5, 2011-03 XC87xCLM Functional Description SSC Error EIR IRCON1.0 EIREN MODIEN.0 Highest Lowest Priority Level 003B SSC Transmit TIR IRCON1.1 TIREN MODIEN.1 >=1 ESSC IEN1.1 RIREN MODIEN.2 H SSC Receive RIR IRCON1.2 IP1.1/ IPH1.1 EINT2 EXINT2 IRCON0.2 EXINT2 EXICON0.4/5 P o l l i n g S e q u e n c e RI UART1 UART1_SCON.0 RIEN UART1_SCON1.0 >=1 TI UART1_SCON.1 TIEN UART1_SCON1.1 Timer 21 Overflow TF2 T21_T2CON.7 TF2EN T21_T2CON1.1 EX2 >=1 >=1 IEN1.2 0043 H IP1.2/ IPH1.2 T21EX EXEN2 EDGES EL T21_T2MOD.5 T21_T2CON.3 EXF2 T21_T2CON.6 EXF2EN T21_T2CON1.0 NDOV UART1_FDCON.2 NDOVEN UART1 Normal Divider Overflow UART1_SCON1.2 CORDIC MDU Result Ready MDU Error EOC CDSTATC.2 IRDY MDUSTAT.0 EA IEN0.7 IERR MDUSTAT.1 Bitaddressable Request flag is cleared by hardware Figure 15 Interrupt Request Sources (Part 3) Data Sheet 64 V1.5, 2011-03 XC87xCLM Functional Description Highest Lowest Priority Level T2CC0/ EINT3 EXINT3 IRCON0.3 EXINT3 EXICON0.6/7 T2CC1/ EINT4 EXINT4 IRCON0.4 EXINT4 EXICON1.0/1 P o l l i n g 004B T2CC2/ EINT5 EXINT5 IRCON0.5 EXM IEN1.3 H IP1.3/ IPH1.3 EXINT5 EXICON1.2/3 >=1 T2CC3/ EINT6 EXINT6 IRCON0.6 S e q u e n c e EXINT6 EXICON1.4/5 Compare Channel 4 CM4F T2CCU_COCON.4 CM4EN MODIEN.3 Compare Channel 5 CM5F T2CCU_COCON.5 CM5EN MODIEN.4 IEN0.7 MultiCAN Node 3 CANSRC3 IRCON2.4 EA Bitaddressable Request flag is cleared by hardware Figure 16 Interrupt Request Sources (Part 4) Data Sheet 65 V1.5, 2011-03 XC87xCLM Functional Description Highest Lowest CCU6 Interrupt node 0 CCU6SR0 IRCON3.0 Priority Level >=1 ECCIP0 IEN1.4 0053 H IP1.4/ IPH1.4 MultiCAN Node 4 CANSRC4 IRCON3.1 CCU6 Interrupt node 1 MultiCAN Node 5 CCU6SR1 IRCON3.4 >=1 ECCIP1 IEN1.5 005B H IP1.5/ IPH1.5 P o l l i n g S e q u e n c e CANSRC5 IRCON3.5 CCU6 Interrupt node 2 MultiCAN Node 6 CCU6SR2 IRCON4.0 >=1 ECCIP2 IEN1.6 0063 CANSRC6 IRCON4.1 H IP1.6/ IPH1.6 CCU6 Interrupt node 3 MultiCAN Node 7 CCU6SRC3 IRCON4.4 >=1 ECCIP3 IEN1.7 CANSRC7 IRCON4.5 006B H IP1.7/ IPH1.7 EA IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 17 Interrupt Request Sources (Part 5) Data Sheet 66 V1.5, 2011-03 XC87xCLM Functional Description 3.4.2 Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the XC87x interrupt sources to the interrupt vector address and the corresponding interrupt node enable bits are summarized in Table 22. Table 22 Interrupt Source NMI Interrupt Vector Addresses Vector Address 0073H Assignment for XC87x Watchdog Timer NMI PLL NMI Flash Timer NMI VDDP Prewarning NMI Flash ECC NMI XINTR0 XINTR1 XINTR2 XINTR3 XINTR4 XINTR5 0003H 000BH 0013H 001BH 0023H 002BH External Interrupt 0 Timer 0 External Interrupt 1 Timer 1 UART T2CCU UART Fractional Divider (Normal Divider Overflow) MultiCAN Node 0 LIN Enable Bit NMIWDT NMIPLL NMIFLASH NMIVDDP NMIECC EX0 ET0 EX1 ET1 ES ET2 IEN0 SFR NMICON Data Sheet 67 V1.5, 2011-03 XC87xCLM Functional Description Table 22 Interrupt Source XINTR6 XINTR7 XINTR8 Interrupt Vector Addresses (cont'd) Vector Address 0033H 003BH 0043H Assignment for XC87x MultiCAN Nodes 1 and 2 ADC[1:0] SSC External Interrupt 2 T21 CORDIC UART1 UART1 Fractional Divider (Normal Divider Overflow) MDU[1:0] XINTR9 004BH External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 T2CCU MultiCAN Node 3 XINTR10 XINTR11 XINTR12 XINTR13 0053H 005BH 0063H 006BH CCU6 INP0 MultiCAN Node 4 CCU6 INP1 MultiCAN Node 5 CCU6 INP2 MultiCAN Node 6 CCU6 INP3 MultiCAN Node 7 ECCIP3 ECCIP2 ECCIP1 ECCIP0 EXM ESSC EX2 Enable Bit EADC SFR IEN1 Data Sheet 68 V1.5, 2011-03 XC87xCLM Functional Description 3.4.3 Interrupt Priority An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by any other interrupt request. If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within each priority level, there is a second priority structure determined by the polling sequence shown in Table 23. Table 23 Source Non-Maskable Interrupt (NMI) External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt UART Interrupt T2CCU,UART Normal Divider Overflow, MultiCAN, LIN Interrupt ADC, MultiCAN Interrupt SSC Interrupt Priority Structure within Interrupt Level Level (highest) 1 2 3 4 5 6 7 8 External Interrupt 2, Timer 21, UART1, UART1 9 Normal Divider Overflow, MDU, CORDIC Interrupt External Interrupt [6:3], MultiCAN Interrupt 10 CCU6 Interrupt Node Pointer 0, MultiCAN interrupt 11 CCU6 Interrupt Node Pointer 1, MultiCAN Interrupt 12 CCU6 Interrupt Node Pointer 2, MultiCAN Interrupt 13 CCU6 Interrupt Node Pointer 3, MultiCAN Interrupt 14 Data Sheet 69 V1.5, 2011-03 XC87xCLM Functional Description 3.5 Parallel Ports The XC87x has 40 port pins organized into five parallel ports: Port 0 (P0), Port 1 (P1), Port 3 (P3), Port 4 (P4) and Port 5 (P5). Each pin has a pair of internal pull-up and pulldown devices that can be individually enabled or disabled. These ports are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Bidirectional Port Features * * * * * * Configurable pin direction Configurable pull-up/pull-down devices Configurable open drain mode Configurable drive strength Transfer of data through digital inputs and outputs (general purpose I/O) Alternate input/output for on-chip peripherals Data Sheet 70 V1.5, 2011-03 XC87xCLM Functional Description Figure 18 shows the structure of a bidirectional port pin. Px_PUDSEL Pull-up/Pull-down Select Register Pull-up/Pull-down Control Logic Internal Bus Px_PUDEN Pull-up/Pull-down Enable Register Px_DS Drive Strength Control Register Px_OD Open Drain Control Register OpenDrain/Output Control Logic Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 Px_ALTSEL1 Alternate Select Register 1 Pull Device 11 10 01 00 AltDataOut 3 AltDataOut 2 AltDataOut1 Output Driver 0 1 Input Driver Pin Px_Data Data Register Out In AltDataIn Schmitt Trigger Pad Figure 18 General Structure of Bidirectional Port Data Sheet 71 V1.5, 2011-03 XC87xCLM Functional Description 3.6 * * Power Supply System with Embedded Voltage Regulator The XC87x microcontroller requires two different levels of power supply: 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports 2.5 V for the core, memory, on-chip oscillator, and peripherals Figure 19 shows the XC87x power supply system. A power supply of 3.3 V or 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regulator and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode1), the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption. CPU & Memory On-chip OSC Peripheral logic ADC VDDC (2.5V) FLASH PLL GPIO Ports (P0-P5) EVR XTAL1& XTAL2 VDDP (3.3V/5.0V) VSSP Figure 19 XC87x Power Supply System EVR Features * * * * * Input voltage (VDDP): 3.3 V/5.0 V Output voltage (VDDC): 2.5 V 7.5% Low power voltage regulator provided in power-down mode1) VDDP prewarning detection VDDC brownout detection 1) SAK product variant does not support power-down mode. Data Sheet 72 V1.5, 2011-03 XC87xCLM Functional Description 3.7 Reset Control The XC87x has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC87x is first powered up, the status of certain pins (see Table 25) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device. The second type of reset in XC87x is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode. 3.7.1 Module Reset Behavior Table 24 lists the functions of the XC87x and the various reset types that affect these functions. The symbol "" signifies that the particular function is reset to its default state. Table 24 Module/ Function CPU Core Peripherals On-Chip Static RAM Oscillator, PLL Port Pins EVR Effect of Reset on Device Functions Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset Not affected, Not affected, Not affected, Affected, un- Affected, unReliable Reliable Reliable reliable reliable The voltage regulator is switched on Disabled Not affected Not affected Not affected FLASH NMI Disabled Data Sheet 73 V1.5, 2011-03 XC87xCLM Functional Description 3.7.2 Booting Scheme When the XC87x is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectively select the different boot options. Table 25 shows the available boot options in the XC87x. Table 25 MBC 1 0 TMS 0 0 XC87x Boot Selection 1) P0.0 X X Type of Mode 2) PC Start Value 0000H User Mode ; on-chip OSC/PLL non-bypassed 0000H BSL Mode; (LIN Mode3), UART/ MultiCAN Mode4)5) and Alternate BSL Mode6)); on-chip OSC/PLL non-bypassed OCDS Mode; on-chip OSC/PLL nonbypassed User (JTAG) Mode7); on-chip OSC/PLL nonbypassed (normal) 0 1 1 1 0 0 0000H 0000H 1) In addition to the pins MBC, TMS and P0.0, TM pin also requires an external pull down for all the boot options. 2) BSL mode is automatically entered if no valid password is installed and data at memory address 0000H equals zero. 3) If a device is programmed as LIN, LIN BSL is always used instead of UART/MultiCAN. 4) UART or MultiCAN BSL is decoded by firmware based on the protocol for product variant with MultiCAN. If no MultiCAN and LIN variant, UART BSL is used. 5) In MultiCAN BSL mode, the clock source is switched to XTAL by firmware, bypassing the on-chip oscillator. This avoids any frequency invariance with the on-chip oscillator and allows other frequency clock input, thus ensuring accurate baud rate detection (especially at high bit rates). 6) Alternate BSL Mode is a user defined BSL code programmed in Flash. It is entered if the AltBSLPassword is valid. 7) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose. Note: The boot options are valid only with the default set of UART and JTAG pins. Data Sheet 74 V1.5, 2011-03 XC87xCLM Functional Description 3.8 Clock Generation Unit The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC87x. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. During user program execution, the frequency can be programmed for an optimal ratio between performance and power consumption. Therefore the power consumption can be adapted to the actual application state. Features * * * * * Phase-Locked Loop (PLL) for multiplying clock source by different factors PLL Base Mode Prescaler Mode PLL Mode Power-down mode support1) The CGU consists of an oscillator circuit and a PLL. In the XC87x, the oscillator can be from either of these two sources: the on-chip oscillator (4 MHz) or the external oscillator (2 MHz to 20 MHz). The term "oscillator" is used to refer to both on-chip oscillator and external oscillator, unless otherwise stated. After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down. 1) SAK product variant does not support power-down mode. Data Sheet 75 V1.5, 2011-03 XC87xCLM Functional Description PLL_LOCK Wrapper PLL lock detect PLL core External oscillator watchdog EXTOSCR OSC fosc NR:1 fp fn fvco OD:1 Switching circuitry fSYS PLLR NF:1 PLL watchdog OSCSS PDIV PLLPD NDIV KDIV PLLBYP Figure 20 CGU Block Diagram Direct Drive (PLL Bypass Operation) During PLL bypass operation, the system clock has the same frequency as the external clock source. (3.1) f SYS = f OSC PLL Mode The CPU clock is derived from the oscillator clock, divided by the NR factor (PDIV), multiplied by the NF factor (NDIV), and divided by the OD factor (KDIV). PLL output must Data Sheet 76 V1.5, 2011-03 XC87xCLM Functional Description not be bypassed for this PLL mode. The PLL mode is used during normal system operation. (3.2) f SYS = f OSC x NF NR x OD System Frequency Selection For the XC87x, the value of NF, NR and OD can be selected by bits NDIV, PDIV and KDIV respectively for different oscillator inputs inorder to obtain the required fsys. But the combination of these factors must fulfill the following condition: * * 100 MHz < fVCO < 175 MHz 800 KHz < fOSC / (2 * NR) < 8 MHz Table 26 provides examples on how the typical system frequency of fsys = 144 MHz and maximum frequency of 160 MHz (CPU clock = 26.67 MHz)can be obtained for the different oscillator sources. Table 26 Oscillator On-chip External System frequency (fsys = 144 MHz) fosc 4 MHz 4 MHz 8 MHz 6 MHz 4 MHz N 72 80 72 72 72 P 2 2 4 3 2 K 1 1 1 1 1 fsys 144 MHz 160 MHz 144 MHz 144 MHz 144 MHz 3.8.1 Recommended External Oscillator Circuits The oscillator circuit, a Pierce oscillator, is designed to work with both, an external crystal oscillator or an external stable clock source. It basically consists of an inverting amplifier and a feedback element with XTAL1 as input, and XTAL2 as output. When using a crystal, a proper external oscillator circuitry must be connected to both pins, XTAL1 and XTAL2. The crystal frequency can be within the range of 2 MHz to 20 MHz. Additionally, it is necessary to have two load capacitances CX1 and CX2, and depending on the crystal type, a series resistor RX2, to limit the current. A test resistor RQ may be temporarily inserted to measure the oscillation allowance (negative resistance) of the oscillator circuitry. RQ values are typically specified by the crystal vendor. An external feedback resistor Rf is also required in the external oscillator circuitry. The exact values and related operating range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative Data Sheet 77 V1.5, 2011-03 XC87xCLM Functional Description resistance method. Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal must be connected to XTAL1. XTAL2 is left open (unconnected). The oscillator can also be used in combination with a ceramic resonator. The final circuitry must also be verified by the resonator vendor. Figure 21 shows the recommended external oscillator circuitries for both operating modes, external crystal mode and external input clock mode. 2 - 20 MHz XTAL1 fOSC External Clock Signal XTAL1 XC87x Oscillator XTAL2 fOSC RQ CX1 Rf RX2 CX2 XC87x Oscillator XTAL2 Fundamental Mode Crystal VSS VSS Figure 21 External Oscillator Circuitry Note: For crystal operation, it is strongly recommended to measure the negative resistance in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the minimum and maximum values of the negative resistance specified by the crystal supplier. Data Sheet 78 V1.5, 2011-03 XC87xCLM Functional Description 3.8.2 Clock Management The CGU generates all clock signals required within the microcontroller from a single clock, fsys. During normal system operation, the typical frequencies of the different modules are as follow: * * * * * * * CPU clock: CCLK, SCLK = 24 MHz MultiCAN clock : MCANCLK = 24 or 48 MHz MDU clock : MDUCLK = 24 or 48 MHz CORDIC clock : CORDICCLK = 24 or 48 MHz CCU6 clock : CCU6CLK = 24 or 48 MHz T2CCU clock : T2CCUCLK = 24 or 48 MHz Peripheral clock: PCLK = 24 MHz In addition, different clock frequencies can be output to pin CLKOUT (P0.0 or P0.7). The clock output frequency, which is derived from the clock output divider (bit COREL), can further be divided by 2 using toggle latch (bit TLEN is set to 1). The resulting output frequency has a 50% duty cycle. Figure 22 shows the clock distribution of the XC87x. Data Sheet 79 V1.5, 2011-03 XC87xCLM Functional Description T2CCFG CCCFG CORDIC CLK CORDIC CCUCCFG MDUCCFG MDU CLK CCU6 CLK MDU FCCFG MCAN CLK CLKREL SD OSCSS External OSC On-chip OSC T2CCU CLK T2CCU CCU6 MultiCAN PCLK 1 FCLK /2 SCLK CCLK Peripherals CORE fosc PLL fsys 0 /3 NF,NR,OD COREL TLEN Toggle Latch CLKOUT COUTS Figure 22 Clock Generation from fsys Data Sheet 80 V1.5, 2011-03 XC87xCLM Functional Description For power saving purposes, the clocks may be disabled or slowed down according to Table 27. Table 27 Idle Slow-down System frequency (fsys = 144 MHz) Action Clock to the CPU is disabled. Clocks to the CPU and all the peripherals are divided by a common programmable factor defined by bit field CMCON.CLKREL. Oscillator and PLL are switched off. Power Saving Mode Power-down1) 1) SAK product variant does not support power-down mode. Data Sheet 81 V1.5, 2011-03 XC87xCLM Functional Description 3.9 Power Saving Modes The power saving modes of the XC87x provide flexible power consumption through a combination of techniques, including: * * * * Stopping the CPU clock Stopping the clocks of individual system components Reducing clock speed of some peripheral components Power-down of the entire system with fast restart capability After a reset, the active mode (normal operating mode) is selected by default (see Figure 23) and the system runs in the main system clock frequency. From active mode, different power saving modes can be selected by software. They are: * * * Idle mode Slow-down mode Power-down mode any interrupt & SD=0 set IDLE bit ACTIVE EXINT0/RXD pin & SD=0 set PD bit IDLE set SD bit clear SD bit POWER-DOWN set IDLE bit any interrupt & SD=1 SLOW-DOWN set PD bit EXINT0/RXD pin & SD=1 Figure 23 Transition between Power Saving Modes Note: SAK product variant does not support power-down mode. Data Sheet 82 V1.5, 2011-03 XC87xCLM Functional Description 3.10 Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must service the WDT within this interval to prevent the WDT from causing an XC87x system reset. Hence, routine service of the WDT confirms that the system is functioning properly. This ensures that an accidental malfunction of the XC87x will be aborted in a user-specified time period. In debug mode, the WDT is default suspended and stops counting. Therefore, there is no need to refresh the WDT during debugging. Features * * * * * 16-bit Watchdog Timer Programmable reload value for upper 8 bits of timer Programmable window boundary Selectable input frequency of fPCLK/2 or fPCLK/128 Time-out detection with NMI generation and reset prewarning activation (after which a system reset will be performed) The WDT is a 16-bit timer incremented by a count rate of fPCLK/2 or fPCLK/128. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8 bits of the WDT can be preset to a user-programmable value via a watchdog service access in order to modify the watchdog expire time period. The lower 8 bits are reset on each service access. Figure 24 shows the block diagram of the WDT unit. WDT Control Clear MUX f PCLK 1:128 WDT Low Byte WDT High Byte WDTREL 1:2 Overflow/Time-out Control & Window-boundary control ENWDT Logic ENWDT_P WDTWINB FNMIWDT WDTRST . WDTIN Figure 24 WDT Block Diagram Data Sheet 83 V1.5, 2011-03 XC87xCLM Functional Description If the WDT is not serviced before the timer overflow, a system malfunction is assumed. As a result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is entered. The prewarning period lasts for 30H count, after which the system is reset (assert WDTRST). The WDT has a "programmable window boundary" which disallows any refresh during the WDT's count-up. A refresh during this window boundary constitutes an invalid access to the WDT, causing the reset prewarning to be entered but without triggering the WDT NMI. The system will still be reset after the prewarning period is over. The window boundary is from 0000H to the value obtained from the concatenation of WDTWINB and 00H. After being serviced, the WDT continues counting up from the value ( The period, PWDT, between servicing the WDT and the next overflow can be determined by the following formula: 2 ( 1 + WDTIN x 6 ) x ( 2 16 - WDTREL x 2 8 ) P WDT = ----------------------------------------------------------------------------------------------------f PCLK (3.3) If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT between servicing the WDT and the next overflow is shortened if WDTWINB is greater than WDTREL, see Figure 25. This period can be calculated using the same formula by replacing WDTREL with WDTWINB. For this feature to be useful, WDTWINB cannot be smaller than WDTREL. Data Sheet 84 V1.5, 2011-03 XC87xCLM Functional Description Count FFFFH WDTWINB WDTREL time No refresh allowed Refresh allowed Figure 25 WDT Timing Diagram Table 28 lists the possible watchdog time ranges that can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 28 Reload value In WDTREL FFH 7FH 00H Watchdog Time Ranges Prescaler for fPCLK 2 (WDTIN = 0) 24 MHz 21.3 s 2.75 ms 5.46 ms 128 (WDTIN = 1) 24 MHz 1.37 ms 176 ms 350 ms Data Sheet 85 V1.5, 2011-03 XC87xCLM Functional Description 3.11 Multiplication/Division Unit The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the XC87x Core in real-time control applications, which require fast mathematical computations. Features * * * * Fast signed/unsigned 16-bit multiplication Fast signed/unsigned 32-bit divide by 16-bit and 16-bit divide by 16-bit operations 32-bit unsigned normalize operation 32-bit arithmetic/logical shift operations Table 29 specifies the number of clock cycles used for calculation in various operations. Table 29 Operation Signed 32-bit/16-bit Signed 16-bit/16bit Signed 16-bit x 16-bit Unsigned 32-bit/16-bit Unsigned 16-bit/16-bit Unsigned 16-bit x 16-bit 32-bit normalize 32-bit shift L/R MDU Operation Characteristics Result 32-bit 16-bit 32-bit 32-bit 16-bit 32-bit Remainder 16-bit 16-bit 16-bit 16-bit 33 17 16 32 16 16 No. of shifts + 1 (Max. 32) No. of shifts + 1 (Max. 32) No. of Clock Cycles used for calculation Data Sheet 86 V1.5, 2011-03 XC87xCLM Functional Description 3.12 CORDIC Coprocessor The CORDIC Coprocessor provides CPU with hardware support for the solving of circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions. Features * Modes of operation - Supports all CORDIC operating modes for solving circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions - Integrated look-up tables (LUTs) for all operating modes Circular vectoring mode: Extended support for values of initial X and Y data up to full range of [-215,(215-1)] for solving angle and magnitude Circular rotation mode: Extended support for values of initial Z data up to full range of [-215,(215-1)], representing angles in the range [-,((215-1)/215)] for solving trigonometry Implementation-dependent operational frequency of up to 80 MHz Gated clock input to support disabling of module 16-bit accessible data width - 24-bit kernel data width plus 2 overflow bits for X and Y each - 20-bit kernel data width plus 1 overflow bit for Z - With KEEP bit to retain the last value in the kernel register for a new calculation 16 iterations per calculation: Approximately 41 clock-cycles or less, from set of start (ST) bit to set of end-of-calculation flag, excluding time taken for write and read access of data bytes. Twos complement data processing - Only exception: X result data with user selectable option for unsigned result X and Y data generally accepted as integer or rational number; X and Y must be of the same data form Entries of LUTs are 20-bit signed integers - Entries of atan and atanh LUTs are integer representations (S19) of angles with the scaling such that [-215,(215-1)] represents the range [-,((215-1)/215)] - Accessible Z result data for circular and hyperbolic functions is integer in data form of S15 Emulated LUT for linear function - Data form is 1 integer bit and 15-bit fractional part (1.15) - Accessible Z result data for linear function is rational number with fixed data form of S4.11 (signed 4Q16) Truncation Error - The result of a CORDIC calculation may return an approximation due to truncation of LSBs - Good accuracy of the CORDIC calculated result data, especially in circular mode Interrupt - On completion of a calculation 87 V1.5, 2011-03 * * * * * * * * * * * * Data Sheet XC87xCLM Functional Description - Interrupt enabling and corresponding flag 3.13 UART and UART1 The XC87x provides two Universal Asynchronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchronous reception/transmission. Both are also receive-buffered, i.e., they can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, one of the bytes will be lost. Features * Full-duplex asynchronous modes - 8-bit or 9-bit data frames, LSB first - Fixed or variable baud rate Receive buffered Multiprocessor communication Interrupt generation on the completion of a data transmission or reception * * * The UART modules can operate in the four modes shown in Table 30. Table 30 UART Modes Baud Rate Operating Mode Mode 0: 8-bit shift register Mode 1: 8-bit shift UART Mode 2: 9-bit shift UART Mode 3: 9-bit shift UART fPCLK/2 Variable fPCLK/32 or fPCLK/641) Variable 1) For UART1 module, the baud rate is fixed at fPCLK/64. There are several ways to generate the baud rate clock for the serial port, depending on the mode in which it is operating. In mode 0, the baud rate for the transfer is fixed at fPCLK/2. In mode 2, the baud rate is generated internally based on the UART input clock and can be configured to eitherfPCLK/32 or fPCLK/64. For UART1 module, only fPCLK/64 is available. The variable baud rate is set by the underflow rate on the dedicated baud-rate generator. For UART module, the variable baud rate alternatively can be set by the overflow rate on Timer 1. 3.13.1 Baud-Rate Generator Both UART modules have their own dedicated baud-rate generator, which is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and Data Sheet 88 V1.5, 2011-03 XC87xCLM Functional Description fractional divider) for generating a wide range of baud rates based on its input clock fPCLK, see Figure 26. Fractional Divider FDSTEP 1 FDM 1 0 FDEN&FDM 8-Bit Reload Value Adder fDIV fMOD (overflow) 0 00 01 11 10 0 1 8-Bit Baud Rate Timer fBR FDEN FDRES R fPCLK Prescaler fDIV clk 11 10 01 `0' 00 NDOV Figure 26 Baud-rate Generator Circuitry The baud rate timer is a count-down timer and is clocked by either the output of the fractional divider (fMOD) if the fractional divider is enabled (FDCON.FDEN = 1), or the output of the prescaler (fDIV) if the fractional divider is disabled (FDEN = 0). For baud rate generation, the fractional divider must be configured to fractional divider mode (FDCON.FDM = 0). This allows the baud rate control run bit BCON.R to be used to start or stop the baud rate timer. At each timer underflow, the timer is reloaded with the 8-bit reload value in register BG and one clock pulse is generated for the serial channel. Enabling the fractional divider in normal divider mode (FDEN = 1 and FDM = 1) stops the baud rate timer and nullifies the effect of bit BCON.R. See Section 3.14. The baud rate (fBR) value is dependent on the following parameters: * * * Input clock fPCLK Prescaling factor (2BRPRE) defined by bit field BRPRE in register BCON Fractional divider (STEP/256) defined by register FDSTEP (to be considered only if fractional divider is enabled and operating in fractional divider mode) 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG * Data Sheet 89 V1.5, 2011-03 XC87xCLM Functional Description The following formulas calculate the final baud rate without and with the fractional divider respectively: f PCLK BRPRE baud rate = ---------------------------------------------------------------------------------- where 2 x ( BR_VALUE + 1 ) > 1 BRPRE 16 x 2 x ( BR_VALUE + 1 ) (3.4) f PCLK STEP baud rate = ---------------------------------------------------------------------------------- x -------------BRPRE 256 16 x 2 x ( BR_VALUE + 1 ) (3.5) The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for a module clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud. Standard LIN protocol can support a maximum baud rate of 20 kHz, the baud rate accuracy is not critical and the fractional divider can be disabled. Only the prescaler is used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of 20 kHz to 57.6 kHz, the higher baud rates require the use of the fractional divider for greater accuracy. Table 31 lists the various commonly used baud rates with their corresponding parameter settings and deviation errors. The fractional divider is disabled and a module clock of 24 MHz is used. Table 31 Baud rate 19.2 kBaud 9600 Baud 4800 Baud 2400 Baud Typical Baud rates for UART with Fractional Divider disabled Prescaling Factor (2BRPRE) 1 (BRPRE=000B) 1 (BRPRE=000B) 2 (BRPRE=001B) 4 (BRPRE=010B) Reload Value (BR_VALUE + 1) 78 (4EH) 156 (9CH) 156 (9CH) 156 (9CH) Deviation Error 0.17 % 0.17 % 0.17 % 0.17 % The fractional divider allows baud rates of higher accuracy (lower deviation error) to be generated. Table 32 lists the resulting deviation errors from generating a baud rate of 57.6 kHz, using different module clock frequencies. The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown. Data Sheet 90 V1.5, 2011-03 XC87xCLM Functional Description Table 32 Deviation Error for UART with Fractional Divider enabled Prescaling Factor Reload Value STEP (2BRPRE) (BR_VALUE + 1) 1 1 1 1 6 (6H) 3 (3H) 2 (2H) 6 (6H) 59 (3BH) 59 (3BH) 59 (3BH) 236 (ECH) Deviation Error +0.03 % +0.03 % +0.03 % +0.03 % fPCLK 24 MHz 12 MHz 8 MHz 6 MHz 3.13.2 Baud Rate Generation using Timer 1 In UART modes 1 and 3 of UART module, Timer 1 can be used for generating the variable baud rates. In theory, this timer could be used in any of its modes. But in practice, it should be set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the required baud rate. The baud rate is determined by the Timer 1 overflow rate and the value of SMOD as follows: x f PCLK 2 Mode 1, 3 baud rate = ---------------------------------------------------32 x 2 x ( 256 - TH1 ) (3.6) SMOD 3.14 Normal Divider Mode (8-bit Auto-reload Timer) Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider mode, while at the same time disables baud rate generation (see Figure 26). Once the fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with no relation to baud rate generation) and counts up from the reload value with each input clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit field STEP in register FDSTEP defines the reload value. At each timer overflow, an overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives an output clock fMOD that is 1/n of the input clock fDIV, where n is defined by 256 - STEP. The output frequency in normal divider mode is derived as follows: 1 f MOD = f DIV x ----------------------------256 - STEP (3.7) Data Sheet 91 V1.5, 2011-03 XC87xCLM Functional Description 3.15 LIN Protocol The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte detection, provides the capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART to be synchronized to the LIN baud rate for data transmission and reception. Note: The LIN baud rate detection feature is available for use only with UART. To use UART1 for LIN communication, software has to be implemented to detect the Break and Synch Byte. LIN is a holistic communication concept for local interconnected networks in vehicles. The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An attractive feature of LIN is self-synchronization of the slave nodes without a crystal or ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the baud rate must be calculated and returned with every message frame. The structure of a LIN frame is shown in Figure 27. The frame consists of the: * * * * Header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field Response time Data bytes (according to UART protocol) Checksum Frame slot Frame Response space Header Response Synch Protected identifier Data 1 Data 2 Data N Checksum Figure 27 Structure of LIN Frame 3.15.1 LIN Header Transmission LIN header transmission is only applicable in master mode. In the LIN communication, a master task decides when and which frame is to be transferred on the bus. It also identifies a slave task to provide the data transported by each frame. The information Data Sheet 92 V1.5, 2011-03 XC87xCLM Functional Description needed for the handshaking between the master and slave tasks is provided by the master task through the header portion of the frame. The header consists of a break and synch pattern followed by an identifier. Among these three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data. The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of frame. For this purpose, every frame starts with a sequence consisting of a break field followed by a synch byte field. This sequence is unique and provides enough information for any slave task to detect the beginning of a new frame and be synchronized at the start of the identifier field. Upon entering LIN communication, a connection is established and the transfer speed (baud rate) of the serial communication partner (host) is automatically synchronized in the following steps: STEP 1: Initialize interface for reception and timer for baud rate measurement STEP 2: Wait for an incoming LIN frame from host STEP 3: Synchronize the baud rate to the host STEP 4: Enter for Master Request Frame or for Slave Response Frame Note: Re-synchronization and setup of baud rate are always done for every Master Request Header or Slave Response Header LIN frame. Data Sheet 93 V1.5, 2011-03 XC87xCLM Functional Description 3.16 High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices or devices using other synchronous serial interfaces. Features * * * Master and slave mode operation - Full-duplex or half-duplex operation Transmit and receive buffered Flexible data format - Programmable number of data bits: 2 to 8 bits - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of the shift clock Variable baud rate Compatible with Serial Peripheral Interface (SPI) Interrupt generation - On a transmitter empty condition - On a receiver full condition - On an error condition (receive, phase, baud rate, transmit error) * * * Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are normally connected to the pin SCLK. Transmission and reception of data are double-buffered. Figure 28 shows the block diagram of the SSC. Data Sheet 94 V1.5, 2011-03 XC87xCLM Functional Description PCLK Baud-rate Generator Clock Control Shift Clock RIR SSC Control Block Register CON TIR EIR SS_CLK MS_CLK Receive Int. Request Transmit Int. Request Error Int. Request Status Control TXD(Master) RXD(Slave) TXD(Slave) RXD(Master) 16-Bit Shift Register Pin Control Transmit Buffer Register TB Receive Buffer Register RB Internal Bus Figure 28 SSC Block Diagram Data Sheet 95 V1.5, 2011-03 XC87xCLM Functional Description 3.17 Timer 0 and Timer 1 Timer 0 and Timer 1 can function as both timers or counters. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are incremented in response to a 1-to-0 transition (falling edge) at their respective external input pins, T0 or T1. Timer 0 and 1 are fully compatible and can be configured in four different operating modes for use in a variety of applications, see Table 33. In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions are specialized. Table 33 Mode 0 Timer 0 and Timer 1 Modes Operation 13-bit timer The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This mode is included solely for compatibility with Intel 8048 devices. 16-bit timer The timer registers, TLx and THx, are concatenated to form a 16-bit counter. 8-bit timer with auto-reload The timer register TLx is reloaded with a user-defined 8-bit value in THx upon overflow. Timer 0 operates as two 8-bit timers The timer registers, TL0 and TH0, operate as two separate 8-bit counters. Timer 1 is halted and retains its count even if enabled. 1 2 3 Data Sheet 96 V1.5, 2011-03 XC87xCLM Functional Description 3.18 Timer 2 and Timer 21 Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode, see Table 34. As a timer, the timers count with an input clock of PCLK/12 (if prescaler is disabled). As a counter, they count 1-to-0 transitions on pin T2. In the counter mode, the maximum resolution for the count is PCLK/24 (if prescaler is disabled). Table 34 Mode Timer 2 Modes Description Auto-reload Up/Down Count Disabled * Count up only * Start counting from 16-bit reload value, overflow at FFFFH * Reload event configurable for trigger by overflow condition only, or by negative/positive edge at input pin T2EX as well * Programmble reload value in register RC2 * Interrupt is generated with reload event Up/Down Count Enabled * Count up or down, direction determined by level at input pin T2EX * No interrupt is generated * Count up - Start counting from 16-bit reload value, overflow at FFFFH - Reload event triggered by overflow condition - Programmble reload value in register RC2 * Count down - Start counting from FFFFH, underflow at value defined in register RC2 - Reload event triggered by underflow condition - Reload value fixed at FFFFH Channel capture * * * * * * * Count up only Start counting from 0000H, overflow at FFFFH Reload event triggered by overflow condition Reload value fixed at 0000H Capture event triggered by falling/rising edge at pin T2EX Captured timer value stored in register RC2 Interrupt is generated with reload or capture event Data Sheet 97 V1.5, 2011-03 XC87xCLM Functional Description 3.19 Timer 2 Capture/Compare Unit The T2CCU (Timer 2 Capture/Compare Unit) consists of the standard Timer 2 unit and a Capture/compare unit (CCU). The Capture/Compare Timer (CCT) is part of the CCU. Control is available in the T2CCU to select individually for each of its 16-bit capture/compare channel, either the Timer 2 or the Capture/Compare Timer (CCT) as the time base. Both timers have a resolution of 16 bits.The clock frequency of T2CCU, fT2CCU, could be set at PCLK frequency or 2 times the PCLK frequency. The T2CCU can be used for various digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. Target applications include various automotive control as well as industrial (frequency generation, digital-to-analog conversion, process control etc.). T2CCU Features * * * * * * * * Option to select individually for each channel, either Timer 2 or Capture/Compare Timer as time base Extremely flexible Capture/Compare Timer count rate by cascading with Timer 2 Capture/Compare Timer may be `reset' immediately by triggering overflow event 16-bit resolution Six compare channels in total Four capture channels multiplexed with the compare channels, in total Shadow register for each compare register - Transfer via software control or on timer overflow. Compare Mode 0: Compare output signal changes from the inactive level to active level on compare match. Returns to inactive level on timer overflow. - Active level can be defined by register bit for channel groups A and B. - Support of 0% to 100% duty cycle in compare mode 0. Compare Mode 1: Full control of the software on the compare output signal level, for the next compare match. Concurrent Compare Mode with channel 0 Capture Mode 0: Capture on any external event (rising/falling/both edge) at the 4 pins T2CC0 to T2CC3. Capture Mode 1: Capture upon writing to the low byte of the corresponding channel capture register. Capture mode 0 or 1 can be established independently on the 4 capture channels. * * * * * Data Sheet 98 V1.5, 2011-03 XC87xCLM Functional Description 3.20 Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and multi-phase machines. The timer T12 can function in capture and/or compare mode for its three channels. The timer T13 can work in compare mode only. The multi-channel control unit generates output patterns, which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation. Timer T12 Features * * * * * * * * * Three capture/compare channels, each channel can be used either as a capture or as a compare channel Supports generation of a three-phase PWM (six outputs, individual signals for highside and lowside switches) 16-bit resolution, maximum count frequency = peripheral clock frequency Dead-time control for each channel to avoid short-circuits in the power stage Concurrent update of the required T12/13 registers Generation of center-aligned and edge-aligned PWM Supports single-shot mode Supports many interrupt request sources Hysteresis-like control mode Timer T13 Features * * * * * One independent compare channel with one output 16-bit resolution, maximum count frequency = peripheral clock frequency Can be synchronized to T12 Interrupt generation at period-match and compare-match Supports single-shot mode Additional Features * * * * * * * Implements block commutation for Brushless DC-drives Position detection via Hall-sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage The block diagram of the CCU6 module is shown in Figure 29. Data Sheet 99 V1.5, 2011-03 XC87xCLM Functional Description module kernel address decoder channel 0 T12 channel 1 channel 2 start compare compare capture compare 1 1 deadtime control multichannel control trap control output select output select 3 clock control 1 T13 interrupt control channel 3 compare 1 3 2 2 2 trap input 1 input / output control CCPOS0 CCPOS1 CCPOS2 COUT63 COUT60 COUT61 COUT62 Hall input compare port control CCU6_block_diagram Figure 29 CCU6 Block Diagram Data Sheet 100 V1.5, 2011-03 CTRAP T12HR T13HR CC60 CC61 CC62 XC87xCLM Functional Description 3.21 Controller Area Network (MultiCAN) The MultiCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B active. Each CAN node can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share a common set of message objects, where each message object may be individually allocated to one of the CAN nodes. Besides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the CAN nodes or to setup a FIFO buffer. The message objects are organized in double chained lists, where each CAN node has it's own list of message objects. A CAN node stores frames only into message objects that are allocated to the list of the CAN node. It only transmits messages from objects of this list. A powerful, command driven list controller performs all list operations. The bit timings for the CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connects each CAN node to a bus transceiver. MultiCAN Module Kernel Interrupt Controller CANSRC[7:0] Clock Control fCAN Message Object Buffer 32 Objects Linked List Control CAN Node 1 CAN Node 0 TXDC1 RXDC1 TXDC0 RXDC0 Port Control Address Decoder & Data control Access Mediator A[13: 2] D[31:0] CAN Control MultiCAN_XC8_overview Figure 30 Features * Overview of the MultiCAN Compliant to ISO 11898. 101 V1.5, 2011-03 Data Sheet XC87xCLM Functional Description * * * * * * CAN functionality according to CAN specification V2.0 B active. Dedicated control registers are provided for each CAN node. A data transfer rate up to 1 MBaud is supported. Flexible and powerful message transfer control and error handling capabilities are implemented. Advanced CAN bus bit timing analysis and baud rate detection can be performed for each CAN node via the frame counter. Full-CAN functionality: A set of 32 message objects can be individually - allocated (assigned) to any CAN node - configured as transmit or receive object - setup to handle frames with 11-bit or 29-bit identifier - counted or assigned a timestamp via a frame counter - configured to remote monitoring mode Advanced Acceptance Filtering: - Each message object provides an individual acceptance mask to filter incoming frames. - A message object can be configured to accept only standard or only extended frames or to accept both standard and extended frames. - Message objects can be grouped into 4 priority classes. - The selection of the message to be transmitted first can be performed on the basis of frame identifier, IDE bit and RTR bit according to CAN arbitration rules. Advanced Message Object Functionality: - Message Objects can be combined to build FIFO message buffers of arbitrary size, which is only limited by the total number of message objects. - Message objects can be linked to form a gateway to automatically transfer frames between 2 different CAN buses. A single gateway can link any two CAN nodes. An arbitrary number of gateways may be defined. Advanced Data Management: - The Message objects are organized in double chained lists. - List reorganizations may be performed any time, even during full operation of the CAN nodes. - A powerful, command driven list controller manages the organization of the list structure and ensures consistency of the list. - Message FIFOs are based on the list structure and can easily be scaled in size during CAN operation. - Static Allocation Commands offer compatibility with TwinCAN applications, which are not list based. Advanced Interrupt Handling: - Up to 8 interrupt output lines are available. Most interrupt requests can be individually routed to one of the 8 interrupt output lines. - Message postprocessing notifications can be flexibly aggregated into a dedicated register field of 64 notification bits. * * * * Data Sheet 102 V1.5, 2011-03 XC87xCLM Functional Description 3.22 Analog-to-Digital Converter The XC87x includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input channels of the ADC are available at AN0 - AN7. Features * * * * * * * * * * * * * * * * * * Successive approximation 8-bit or 10-bit resolution Eight analog channels Four independent result registers Result data protection for slow CPU access (wait-for-read mode) Single conversion mode Autoscan functionality Limit checking for conversion results Data reduction filter (accumulation of up to 2 conversion results) Two independent conversion request sources with programmable priority Selectable conversion request trigger Flexible interrupt generation with configurable service nodes Programmable sample time Programmable clock divider Cancel/restart feature for running conversions Integrated sample and hold circuitry Compensation of offset errors Low power modes 3.22.1 ADC Clocking Scheme A common module clock fADC generates the various clock signals used by the analog and digital parts of the ADC module: * * fADCA is input clock for the analog part. fADCI is internal clock for the analog part (defines the time base for conversion length * and the sample time). This clock is generated internally in the analog part, based on the input clock fADCA to generate a correct duty cycle for the analog components. fADCD is input clock for the digital part. Figure 31 shows the clocking scheme of the ADC module. The prescaler ratio is selected by bit field CTC in register GLOBCTR. A prescaling ratio of 32 can be selected when the maximum performance of the ADC is not required. Data Sheet 103 V1.5, 2011-03 XC87xCLM Functional Description fADC = fPCLK fADCD arbiter registers interrupts digital part fADCA CTC / 32 /4 /3 /2 MUX fADCI analog components clock prescaler analog part Figure 31 ADC Clocking Scheme For module clock fADC = 24 MHz, the analog clock fADCI frequency can be selected as shown in Table 35. Table 35 24 MHz fADCI Frequency Selection CTC 00B 01B 10B 11B (default) Prescaling Ratio /2 /3 /4 / 32 Analog Clock fADCI 12 MHz 8 MHz 6 MHz 750 kHz Module Clock fADC During slow-down mode, fADC may be reduced further, for example, to 12 MHz or 6 MHz. However, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if fADC becomes too low during slow-down mode. 3.22.2 ADC Conversion Sequence The analog-to-digital conversion procedure consists of the following phases: Data Sheet 104 V1.5, 2011-03 XC87xCLM Functional Description * * * * Synchronization phase (tSYN) Sample phase (tS) Conversion phase Write result phase (tWR) conversion start trigger Sample Phase fADCI BUSY Bit SAMPLE Bit tSYN tS tCONV Write Result Phase tWR Conversion Phase Source interrupt Channel interrupt Result interrupt Figure 32 ADC Conversion Timing Data Sheet 105 V1.5, 2011-03 XC87xCLM Functional Description 3.23 On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: * * * * Use the built-in debug functionality of the XC800 Core Add a minimum of hardware overhead Provide support for most of the operations by a Monitor Program Use standard interfaces to communicate with the Host (a Debugger) Features * * * * * Set breakpoints on instruction address and on address range within the Program Memory Set breakpoints on internal RAM address range Support unlimited software breakpoints in Flash/RAM code region Process external breaks via JTAG and upon activating a dedicated pin Step through the program code The OCDS functional blocks are shown in Figure 33. The Monitor Mode Control (MMC) block at the center of OCDS system brings together control signals and supports the overall functionality. The MMC communicates with the XC800 Core, primarily via the Debug Interface, and also receives reset and clock signals. After processing memory address and control signals from the core, the MMC provides proper access to the dedicated extra-memories: a Monitor ROM (holding the code) and a Monitor RAM (for work-data and Monitor-stack). The OCDS system is accessed through the JTAG1), which is an interface dedicated exclusively for testing and debugging activities and is not normally used in an application. The dedicated MBC pin is used for external configuration and debugging control. Note: All the debug functionality described here can normally be used only after XC87x has been started in OCDS mode. 1) The pins of the JTAG port can be assigned to either the primary port (Port 0) or either of the secondary ports (Ports 1 and 2/Port 5). User must set the JTAG pins (TCK and TDI) as input during connection with the OCDS system. Data Sheet 106 V1.5, 2011-03 XC87xCLM Functional Description JTAG Module Debug Interface TMS TCK TDI TDO TCK TDI TDO Control Reset JTAG Memory Control Unit User Program Memory Boot/ Monitor ROM Monitor Mode Control Monitor & Bootstrap loader Control line MBC User Internal RAM Suspend Control Reset Clock Monitor RAM System Control Unit - parts of OCDS Reset Clock Debug PROG PROG Memory Interface & IRAM Data Control Addresses XC800 Core OCDS_XC886C-Block_Diagram-UM-v0.2 Figure 33 OCDS Block Diagram 3.23.1 JTAG ID Register This is a read-only register located inside the JTAG module, and is used to recognize the device(s) connected to the JTAG interface. Its content is shifted out when INSTRUCTION register contains the IDCODE command (opcode 04H), and the same is also true immediately after reset. The JTAG ID register contents for the XC87x Flash devices are given in Table 36. Table 36 Device Type Flash JTAG ID Summary Device Name XC87x*-16FF XC87x*-13FF JTAG ID 1018 2083H 1018 3083H Note: The asterisk (*) above denotes all possible device configurations. Data Sheet 107 V1.5, 2011-03 XC87xCLM Functional Description 3.24 Chip Identification Number The XC87x identity (ID) register is located at Page 1 of address B3H. The value of ID register is 49H. However, for easy identification of product variants, the Chip Identification Number, which is an unique number assigned to each product variant, is available. The differentiation is based on the product, variant type and device step information. Two methods are provided to read a device's chip identification number: * * In-application subroutine, GET_CHIP_INFO Bootstrap loader (BSL) mode A Table 37 lists the chip identification numbers of available XC87x Flash device variants. Table 37 Chip Identification Number Chip Identification Number AC-step Flash Devices XC878-16FF 5V XC878M-16FF 5V XC878CM-16FF 5V XC878LM-16FF 5V XC878CLM-16FF 5V XC878-13FF 5V XC878M-13FF 5V XC878CM-13FF 5V XC878LM-13FF 5V XC878CLM-13FF 5V XC878-16FF 3V3 XC878M-16FF 3V3 XC878CM-16FF 3V3 XC878-13FF 3V3 XC878M-13FF 3V3 XC878CM-13FF 3V3 XC874CM-16FV 5V XC874LM-16FV 5V XC874-16FV 5V Data Sheet Product Variant 4B580063H 4B580023H 4B580003H 4B500023H 4B500003H 4B590463H 4B590423H 4B590403H 4B510423H 4B510403H 4B180063H 4B180023H 4B180003H 4B190463H 4B190423H 4B190403H 4B580002H 4B500022H 4B580062H 108 V1.5, 2011-03 XC87xCLM Functional Description Table 37 Chip Identification Number (cont'd) Chip Identification Number AC-step XC874CM-13FV 5V XC874LM-13FV 5V XC874-13FV 5V 4B590402H 4B510422H 4B590462H Product Variant Data Sheet 109 V1.5, 2011-03 XC87xCLM Electrical Parameters 4 Electrical Parameters Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the XC87x. 4.1 General Parameters The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 and Section 4.3. 4.1.1 Parameter Interpretation The parameters listed in this section represent partly the characteristics of the XC87x and partly its requirements on the system. To aid interpreting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the "Symbol" column: * CC These parameters indicate Controller Characteristics, which are distinctive features of the XC87x and must be regarded for a system design. SR These parameters indicate System Requirements, which must be provided by the microcontroller system in which the XC87x is designed in. * Data Sheet 108 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.1.2 Absolute Maximum Rating Maximum ratings are the extreme limits to which the XC87x can be subjected to without permanent damage. Table 38 Parameter Ambient temperature Absolute Maximum Rating Parameters Symbol -40 -65 -40 -0.5 -0.5 Limit Values min. max. 125 150 140 6 VDDP + 0.5 or max. 6 10 50 C C C V V Whatever is lower under bias under bias Unit Notes TA Storage temperature TST Junction temperature TJ Voltage on power supply pin with VDDP respect to VSS Voltage on any pin with respect to VSS VIN Input current on any pin during overload condition IIN -10 - mA mA Absolute sum of all input currents |IIN| during overload condition Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDDP or VIN < VSS) the voltage on VDDP pin with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 109 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.1.3 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the XC87x. All parameters mentioned in the following table refer to these operating conditions, unless otherwise noted. Table 39 Parameter Digital power supply voltage Digital power supply voltage Digital ground voltage CPU Clock Frequency1) Ambient temperature Operating Condition Parameters Symbol Limit Values min. max. 5.5 3.6 26.672) -40 -40 -40 2)Default setting of fCCLK upon reset is 24 MHz. 85 105 125 4.5 3.0 0 Unit Notes/ Conditions V V V MHz C C C SAF-XC878/874... SAX-XC878... SAK-XC878/874... 5V Device 3.3V Device VDDP VDDP VSS fCCLK TA 1) fCCLK is the input frequency to the XC800 core. Please refer to Figure 22 for detailed description. Data Sheet 110 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.2 DC Parameters The electrical characteristics of the DC Parameters are detailed in this section. 4.2.1 Input/Output Characteristics Table 40 provides the characteristics of the input/output pins of the XC87x. Table 40 Parameter Input/Output Characteristics (Operating Conditions apply) Symbol Limit Values min. max. 0.6 - 0.8 V V V V V V V A A A A A mA mA V 5) Unit Test Conditions VDDP = 5 V Range Output low voltage Output high voltage Input low voltage Input high voltage Input Hysteresis Input low voltage at XTAL1 Input high voltage at XTAL1 Pull-up current Pull-down current Input leakage current Overload current on any pin Absolute sum of overload currents Voltage on any pin during VDDP power off VOL VOH VIL VIH HYS VILX VIHX IPU IPD IOZ1 IOV |IOV| CC - CC 2.4 SR -0.3 SR 2.2 CC 0.35 SR -0.3 SR 3.4 SR - -88 SR - 66 CC -1 SR -5 SR - SR - IOL = 9 mA (DS = 0)1) IOL = 12 mA (DS = 1)2) IOH = -20 mA (DS = 0)1) IOH = -25 mA (DS = 1)2) CMOS Mode CMOS Mode CMOS Mode3)7) VDDP - 0.8 VDDP -20 - 10 - 1 5 25 0.3 VIH,min VIL,max VIL,max VIH,min 0 < VIN < VDDP, TA 105C4) VPO 6) Data Sheet 111 V1.5, 2011-03 XC87xCLM Electrical Parameters Table 40 Parameter Maximum current per pin (excluding VDDP and VSS) Maximum current for all pins (excluding VDDP and VSS) Maximum current into Input/Output Characteristics (Operating Conditions apply) (cont'd) Symbol Limit Values min. max. 25 mA Unit Test Conditions IM SR SR - |IM| SR - 150 mA VDDP Maximum current out of VSS IMVDDP SR - IMVSS SR - 200 200 mA mA 5) 5) VDDP = 3.3 V Range Output low voltage Output high voltage Input low voltage Input high voltage Input Hysteresis Input low voltage at XTAL1 Input high voltage at XTAL1 Pull-up current Pull-down current Input leakage current Overload current on any pin Absolute sum of overload currents VOL VOH VIL VIH HYS VILX VIHX IPU IPD IOZ1 IOV |IOV| CC - CC 2.2 SR -0.3 SR 2 CC 0.28 SR -0.3 SR 2.3 SR - -35 SR - 60 CC -1 SR -5 SR - 0.5 - 0.7 V V V V V V V A A A A A mA mA IOL = 6 mA (DS = 0)1) IOL = 8 mA (DS = 1)2) IOH = -5 mA (DS = 0)1) IOH = -7 mA (DS = 1)2) CMOS Mode CMOS Mode CMOS Mode3)7) VDDP - 0.7 VDDP -7 - 12 - 1 5 25 VIH,min VIL,max VIL,max VIH,min 0 < VIN < VDDP, TA 105C4) 5) Data Sheet 112 V1.5, 2011-03 XC87xCLM Electrical Parameters Table 40 Parameter Voltage on any pin during VDDP power off Maximum current per pin (excluding VDDP and VSS) Maximum current for all pins (excluding VDDP and VSS) Maximum current into Input/Output Characteristics (Operating Conditions apply) (cont'd) Symbol Limit Values min. max. 0.3 8 V mA 6) Unit Test Conditions VPO SR - IM SR SR - |IM| SR - 150 mA VDDP Maximum current out of VSS IMVDDP SR - IMVSS SR - 200 200 mA mA 5) 5) 1) DS = 0 refers to the pin having a weak drive strength which is programmable via Px_DS register. 2) DS = 1 refers to the pin having a strong drive strength which is programmable via Px_DS register. 3) Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot be guaranteed that it suppresses switching due to external system noise. 4) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin. TMS pin and RESET pin have internal pull devices and are not included in the input leakage current characteristic. 5) Not subjected to production test, verified by design/characterization. 6) Not subjected to production test, verified by design/characterization. However, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any GPIO pin when VDDP is powered off. 7) P0.1 has a minimum input hysteresis of 0.25V. Data Sheet 113 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.2.2 Supply Threshold Characteristics Table 41 provides the characteristics of the supply threshold in the XC87x. 5.0V VDDPPW VDDP 2.5V VDDC VDDCPOR V DDCBO VDDCRDR Figure 34 Table 41 Parameters Supply Threshold Parameters Supply Threshold Parameters (Operating Conditions apply) Symbol min. 1) Limit Values typ. 1.9 - 4.2 1.9 max. 2.2 - 4.5 2.2 CC CC CC CC 1.7 1.2 3.8 1.7 Unit V V V V VDDC brownout voltage RAM data retention voltage VDDP prewarning voltage2) Power-on reset voltage1)3) VDDCBO VDDCRDR VDDPPW VDDCPOR 1) Detection is enabled in both active and power-down mode. 2) Detection is enabled for 5.0V power supply variant. Detection is disabled for 3.3V power supply variant. 3) The reset of EVR is extended by 300 s typically after the VDDC reaches the power-on reset voltage. Data Sheet 114 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.2.3 ADC Characteristics The values in the table below are given for an analog power supply between 4.5 V to 5.5 V. The ADC can be used with an analog power supply down to 3 V. But in this case, the analog parameters may show a reduced performance. All ground pins (VSS) must be externally connected to one single star point in the system. The voltage difference between the ground pins must not exceed 200mV. Table 42 Parameter Analog reference voltage Analog reference ground Analog input voltage range ADC clocks ADC Characteristics (Operating Conditions apply; VDDP = 5V Range) Symbol Limit Values min. typ . max. SR VAGND VDDP +1 SR VSS 0.05 Unit Test Conditions/ Remarks V 1) VAREF VAGND VAIN fADC fADCI tS VDDP + 0.05 1) VSS -1 VAREF V VAREF V SR VAGND - - - 24 - - 142) MHz module clock1) MHz internal analog clock1) See Figure 31 1) Sample time Conversion time Differential Nonlinearity Integral Nonlinearity Offset Gain Switched capacitance at the reference voltage input Switched capacitance at the analog voltage inputs CC (2 + INPCR0.STC) x s tADCI 1) tC CC See Section 4.2.3.1 s |EADNL| CC - - 1.5 LSB 10-bit conversion |EAINL| CC - - - - 10 2 3 2.5 14 LSB 10-bit conversion LSB 10-bit conversion LSB 10-bit conversion pF 1)3) |EAOFF| CC - |EAGAIN| CC - CAREFSW CC - CAINSW CC - 4 5 pF 1)4) Data Sheet 115 V1.5, 2011-03 XC87xCLM Electrical Parameters Table 42 Parameter ADC Characteristics (Operating Conditions apply; VDDP = 5V Range) Symbol CC - CC - Limit Values min. Input resistance of RAREF the reference input Input resistance of RAIN the selected analog channel typ . 1 1 max. 2 3 Unit Test Conditions/ Remarks k k 1) 1) 1) Not subjected to production test, verified by design/characterization. 2) This value includes the maximum oscillator deviation. 3) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this, smaller capacitances are successively switched to the reference voltage. 4) The sampling capacity of the conversion C-Network is pre-charged to VAREF/2 before connecting the input to the C-Network. Because of the parasitic elements, the voltage measured at ANx is lower than VAREF/2. Data Sheet 116 V1.5, 2011-03 XC87xCLM Electrical Parameters Analog Input Circuitry REXT ANx RAIN, On VAIN CEXT VAGNDx C AINSW Reference Voltage Input Circuitry VAREFx R AREF, On VAREF VAGNDx C AREFSW Figure 35 ADC Input Circuits 4.2.3.1 ADC Conversion Timing Conversion time, tC = tADC x ( 1 + r x (3 + n + STC) ) , where r = CTC + 2 for CTC = 00B, 01B or 10B, r = 32 for CTC = 11B, CTC = Conversion Time Control (GLOBCTR.CTC), STC = Sample Time Control (INPCR0.STC), n = 8 or 10 (for 8-bit and 10-bit conversion respectively), tADC = 1 / fADC Data Sheet 117 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.2.4 Power Supply Current Table 43, Table 44, Table 45 and Table 46 provide the characteristics of the power supply current in the XC87x. Table 43 Parameter Power Supply Current Parameters (Operating Conditions apply; VDDP = 5V range) Symbol Limit Values typ.1) max.2) 45 48 35 38 15 18 14 17 mA mA mA mA mA mA mA mA 3) 3) 4) 4) 5) 5) 6) 6) Unit Test Conditions VDDP = 5V Range Active Mode Idle Mode Active Mode with slowdown enabled Idle Mode with slowdown enabled IDDP IDDP IDDP IDDP 37.5 40.5 29.2 32.2 10 13 9.2 12.2 SAF and SAX variants SAK variant SAF and SAX variants SAK variant SAF and SAX variants SAK variant SAF and SAX variants SAK variant 1) The typical IDDP values are based on preliminary measurements and are to be used as reference only. These values are periodically measured at TA = + 25 C and VDDP = 5.0 V. 2) The maximum IDDP values are measured under worst case conditions (TA = + 105 C and VDDP = 5.5 V). 3) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz with onchip oscillator of 4 MHz, RESET = VDDP; all other pins are disconnected, no load on ports. 4) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz, RESET = VDDP; all other pins are disconnected, no load on ports. 5) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no load on ports. 6) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no load on ports. Data Sheet 118 V1.5, 2011-03 XC87xCLM Electrical Parameters Table 44 Parameter Power Down Current1)(Operating Conditions apply; VDDP = 5V range) Symbol Limit Values typ.2) max.3) 80 250 A A Unit Test Conditions VDDP = 5V Range Power-Down Mode IPDP 20 - TA = + 25 C4)5) TA = + 85 C5)6) 1) The table is only applicable to SAF and SAX variants. SAK variant does not support power-down mode 2) The typical IPDP values are based on preliminary measurements and are to be used as reference only. These values are measured at VDDP = 5.0 V. 3) The maximum IPDP values are measured at VDDP = 5.5 V. 4) IPDP has a maximum value of 450 A at TA = + 105 C. 5) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. 6) Not subjected to production test, verified by design/characterization. Data Sheet 119 V1.5, 2011-03 XC87xCLM Electrical Parameters Table 45 Parameter Power Supply Current Parameters1) (Operating Conditions apply; VDDP = 3.3V range) Symbol Limit Values typ.2) max.3) 43 33 13 12 Unit Test Conditions mA mA mA mA 4) 5) 6) VDDP = 3.3V Range Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled IDDP IDDP IDDP IDDP 35.4 27.6 8.6 8 7) 1) The table is only applicable to SAF and SAX variants. 2) The typical IDDP values are based on preliminary measurements and are to be used as reference only. These values are periodically measured at TA = + 25 C and VDDP = 3.3 V. 3) The maximum IDDP values are measured under worst case conditions (TA = + 105 C and VDDP = 3.6 V). 4) IDDP (active mode) is measured with: CPU clock and input clock to all peripherals running at 24 MHz with onchip oscillator of 4 MHz, RESET = VDDP; all other pins are disconnected, no load on ports. 5) IDDP (idle mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 MHz, RESET = VDDP; all other pins are disconnected, no load on ports. 6) IDDP (active mode with slow-down mode) is measured with: CPU clock and input clock to all peripherals running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no load on ports. 7) IDDP (idle mode with slow-down mode) is measured with: CPU clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 1 MHz by setting CLKREL in CMCON to 1000B, RESET = VDDP; all other pins are disconnected, no load on ports. Data Sheet 120 V1.5, 2011-03 XC87xCLM Electrical Parameters Table 46 Parameter Power Down Current1)(Operating Conditions apply; VDDP = 3.3V range) Symbol Limit Values typ.2) max.3) 80 250 A A Unit Test Conditions VDDP = 3.3V Range Power-Down Mode IPDP 20 - TA = + 25 C4)5) TA = + 85 C5)6) 1) The table is only applicable to SAF and SAX variants. 2) The typical IPDP values are based on preliminary measurements and are to be used as reference only. These values are measured at VDDP = 3.3 V. 3) The maximum IPDP values are measured at VDDP = 3.6 V. 4) IPDP has a maximum value of 450 A at TA = + 105 C. 5) IPDP is measured with: RESET = VDDP, VAGND= VSS, RXD/INT0 = VDDP; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. 6) Not subjected to production test, verified by design/characterization. Data Sheet 121 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.3 AC Parameters The electrical characteristics of the AC Parameters are detailed in this section. 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 36, Figure 37 and Figure 38. VDDP 90% 90% VSS 10% tR tF 10% Figure 36 Rise/Fall Time Parameters VDDP VDDE / 2 VSS Test Points VDDE / 2 Figure 37 Testing Waveform, Output Delay VLoad + 0.1 V VLoad - 0.1 V Timing Reference Points VOH - 0.1 V VOL - 0.1 V Figure 38 Testing Waveform, Output High Impedance Data Sheet 122 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.3.2 Output Rise/Fall Times Table 47 provides the characteristics of the output rise/fall times in the XC87x. Table 47 Parameter Output Rise/Fall Times Parameters (Operating Conditions apply) Symbol Limit Values min. max. Unit Test Conditions VDDP = 5V Range Rise/fall times t R , tF t R , tF - - 10 10 ns ns 20 pF.1) 2)3) 20 pF.1) 2)4) VDDP = 3.3V Range Rise/fall times 1) Rise/Fall time measurements are taken with 10% - 90% of pad supply. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 3) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.125 ns/pF. 4) Additional rise/fall time valid for CL = 20pF - 100pF @ 0.225 ns/pF. V DDP 90% 10% tF 90% 10% VSS tR Figure 39 Rise/Fall Times Parameters Data Sheet 123 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.3.3 Power-on Reset and PLL Timing Table 48 provides the characteristics of the power-on reset and PLL timing in the XC87x. Table 48 Parameter On-Chip Oscillator start-up time PLL lock-in in time Power-On Reset and PLL Timing (Operating Conditions apply) Symbol Limit Values min. typ. max. 500 200 1.8 ns s ns 1) Unit Test Conditions tOSCST CC - CC - - - - - tLOCK PLL accumulated jitter DP 1) 1)2) 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 2) PLL lock at 144 MHz using a 4 MHz external oscillator. The PLL Divider settings are K = 2, N = 72 and P = 1. VDDP VDDC VPAD tOSCST OSC PLL PLL unlock t LOCK PLL lock Pads 2)Pull/Input 3)As Programmed 1) Pad state undefined I)until EVR is stable II)until PLL is locked III) Reset is released and start of program Figure 40 Power-on Reset Timing Data Sheet 124 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.3.4 On-Chip Oscillator Characteristics Table 49 provides the characteristics of the on-chip oscillator in the XC87x. Table 49 Parameter Nominal frequency On-chip Oscillator Characteristics (Operating Conditions apply) Symbol Limit Values min. typ. max. 3.88 4 4.12 Unit Test Conditions MHz under nominal conditions1) after IFX-backend trimming % with respect to fNOM, over lifetime and temperature (-40C to 105C), for one given device after trimming within one LIN message (<10 ms .... 100 ms) fNOM CC Long term frequency fLT deviation CC -5 - 5 Short term frequency fST CC deviation -1.0 - 1.0 % 1) Nominal condition: VDDC = 2.5 V, TA = + 25C. Data Sheet 125 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.3.5 External Data Memory Characteristics Table 50 shows the timing of the external data memory read cycle. Table 50 Parameter RD pulse width External Data Memory Read Timing1) (Operating Conditions apply) Symbol Min. Limit Values Max. 3*fCCLK - 7 ns ns ns ns Unit Test Conditions 2) 2) 2) 2) 2) t1 Address valid to RD t2 RD to valid data in t3 Address to valid data in t4 Data hold after RD t5 CC 2*fCCLK - 17 CC fCCLK - 12 SR SR - 1.5*fCCLK - 27 ns SR 0.5*fCCLK -17 - 1) External Bus Interface is not available in XC874. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Addresses DATA ADDRESS t1 RD t2 D[7:0] t4 t3 VALID t5 Figure 41 External Data Memory Read Cycle Data Sheet 126 V1.5, 2011-03 XC87xCLM Electrical Parameters Table 51 shows the timing of the external data memory write cycle. Table 51 Parameter WR pulse width External Data Memory Write Timing1) (Operating Conditions apply) Symbol Min. Limit Values Max. ns ns ns ns ns Unit Test Conditions 2) 2) 2) 2) 2) t1 Address valid to WR t2 Data valid to WR transition t3 Data setup before WR t4 Data hold after WR t5 CC fCCLK - 10 CC 2*fCCLK - 7 SR fCCLK - 5 SR 9*fCCLK - 13 SR 6*fCCLK - 3 1) External Bus Interface is not available in XC874. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. Addresses t2 WR t3 D[7:0] DATA ADDRESS t1 t5 VALID t4 Figure 42 External Data Memory Write Cycle Data Sheet 127 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.3.6 External Clock Drive XTAL1 Table 52 shows the parameters that define the external clock supply for XC87x. These timing parameters are based on the direct XTAL1 drive of clock input signals. They are not applicable if an external crystal or ceramic resonator is considered. Table 52 Parameter Oscillator period High time Low time Rise time Fall time External Clock Drive Characteristics (Operating Conditions apply) Symbol Limit Values Min. Max. 500 10 10 ns ns ns ns ns 1)2) 2)3) 2)3) 2)3) 2)3) Unit Test Conditions tosc t1 t2 t3 t4 SR 50 SR 15 SR 15 SR SR - 1) The clock input signals with 45-55% duty cycle are used. 2) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 3) The clock input signal must reach the defined levels VILX and VIHX. t1 0.5 V DDC t2 tOSC t3 t4 VIHX VILX Figure 43 External Clock Drive XTAL1 Data Sheet 128 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.3.7 JTAG Timing Table 53 provides the characteristics of the JTAG timing in the XC87x. Table 53 Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time TCK Clock Timing (Operating Conditions apply; CL = 50 pF) Symbol Limits min max 4 4 ns ns ns ns ns 1) 1) 1) 1) 1) Unit Test Conditions tTCK t1 t2 t3 t4 SR SR SR SR SR 50 20 20 - 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. 0.5 V DDP 0.9 V DDP 0.1 V DDP TCK t1 t TCK t2 t4 t3 Figure 44 Table 54 Parameter TCK Clock Timing JTAG Timing (Operating Conditions apply; CL = 50 pF) Symbol Limits min max 24 31 ns ns ns ns ns ns 1) Unit Test Conditions TMS setup to TCK TMS hold to TCK TDI setup to TCK TDI hold to TCK TDO valid output from TCK t1 t2 t1 t2 t3 SR SR SR SR CC 8 0 8 4 - 1) 1) 1) 5V Device1) 3.3V Device1) Data Sheet 129 V1.5, 2011-03 XC87xCLM Electrical Parameters Table 54 Parameter JTAG Timing (Operating Conditions apply; CL = 50 pF) (cont'd) Symbol CC CC Limits min TDO high impedance to valid t4 output from TCK TDO valid output to high impedance from TCK max 18 21 21 20 ns ns ns ns 5V Device1) 3.3V Device1) 5V Device1) 3.3V Device1) Unit Test Conditions t5 1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation. TCK t1 t2 TMS t1 t2 TDI t4 t3 t5 TDO Figure 45 JTAG Timing Data Sheet 130 V1.5, 2011-03 XC87xCLM Electrical Parameters 4.3.8 SSC Master Mode Timing Table 55 provides the characteristics of the SSC timing in the XC87x. Table 55 Parameter SCLK clock period MTSR delay from SCLK MRST setup to SCLK MRST hold from SCLK SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) Symbol Limit Values min. max. - 5 - - ns ns ns ns 1)2) 2) Unit Test Conditions t0 t1 t2 t3 CC CC SR SR 2*TSSC 0 13 0 2) 2) 1) TSSCmin = TCPU = 1/fCPU. When fCPU = 24 MHz, t0 = 83.3ns. TCPU is the CPU clock period. 2) 1Not all parameters are 100% tested, but are verified by design/characterization and test correlation. t0 SCLK1) t1 MTSR1) t1 t2 t3 Data valid MRST1) t1 1) This timing is based on the following setup: CON.PH = CON.PO = 0. SSC_Tmg1 Figure 46 SSC Master Mode Timing Data Sheet 131 V1.5, 2011-03 XC87xCLM Package and Quality Declaration 5 Package and Quality Declaration Chapter 5 provides the information of the XC87x package and reliability section. 5.1 Package Parameters Table 56 provides the thermal characteristics of the package used in XC878 and XC874. Table 56 Parameter PG-LQFP-64-4 (XC878) Thermal resistance junction RTJC case1) Thermal resistance junction RTJL lead1) PG-VQFN-48-22 (XC874) Thermal resistance junction RTJC case1) Thermal resistance junction RTJL lead1) CC CC 16.6 30.7 K/W K/W CC CC 13.8 34.6 K/W K/W Thermal Characteristics of the Packages Symbol Min. Limit Values Max. Unit Notes 1) The thermal resistances between the case and the ambient (RTCA) , the lead and the ambient (RTLA) are to be combined with the thermal resistances between the junction and the case (RTJC), the junction and the lead (RTJL) given above, in order to calculate the total thermal resistance between the junction and the ambient (RTJA). The thermal resistances between the case and the ambient (RTCA), the lead and the ambient (RTLA) depend on the external system (PCB, case) characteristics, and are under user responsibility. The junction temperature can be calculated using the following equation: TJ=TA+RTJA x PD, where the RTJA is the total thermal resistance between the junction and the ambient. This total junction ambient resistance RTJA can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. Data Sheet 133 V1.5, 2011-03 XC87xCLM Package and Quality Declaration 5.2 Package Outline Figure 47 shows the package outlines of the XC878. Figure 47 PG-LQFP-64-4 Package Outline Data Sheet 134 V1.5, 2011-03 XC87xCLM Package and Quality Declaration Figure 48 shows the package outlines of the XC874. Figure 48 PG-VQFN-48-22 Package Outline Data Sheet 135 V1.5, 2011-03 XC87xCLM Package and Quality Declaration 5.3 Quality Declaration Table 57 shows the characteristics of the quality parameters in the XC87x. Table 57 Parameter Operation Lifetime when the device is used at the two stated TJ1) Operation Lifetime when the device is used at the five stated TJ1) Quality Parameters Symbol Limit Values Min. Max. 15000 2000 120 960 7800 2400 720 2000 hours hours hours hours hours hours hours V TJ = 110C TJ = -40C TJ = 140C TJ = 135C TJ = 91C TJ = 38C TJ = -25C Conforming to EIA/JESD22A114-B Conforming to JESD22-C101-C Unit Notes tOP1 tOP2 - ESD susceptibility VHBM according to Human Body Model (HBM) ESD susceptibility according to Charged Device Model (CDM) pins - VCDM - 750 V 1) This lifetime refers only to the time when device is powered-on. Data Sheet 136 V1.5, 2011-03 www.infineon.com Published by Infineon Technologies AG |
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